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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-01-16 10:04:42 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-01-16 23:21:56 -0600 |
| commit | c8c41d4a80b1a8ad5984a287d81ea780496259f8 (patch) | |
| tree | d16801f7e70a98bc8f7f636bc458ccbc087bbe0c /board/freescale/mpc8540ads | |
| parent | 54a5070115eff38e9b324b78abdfa0b4520580b9 (diff) | |
| download | u-boot-imx-c8c41d4a80b1a8ad5984a287d81ea780496259f8.zip u-boot-imx-c8c41d4a80b1a8ad5984a287d81ea780496259f8.tar.gz u-boot-imx-c8c41d4a80b1a8ad5984a287d81ea780496259f8.tar.bz2 | |
85xx: Use proper defines for PCI addresses
We should be using the _MEM_PHYS for LAW and TLB setup and not _MEM_BASE.
While _MEM_BASE & _MEM_PHYS are normally the same, _MEM_BASE should only
be used for configuring the PCI ATMU.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/mpc8540ads')
| -rw-r--r-- | board/freescale/mpc8540ads/init.S | 8 | ||||
| -rw-r--r-- | board/freescale/mpc8540ads/law.c | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/board/freescale/mpc8540ads/init.S b/board/freescale/mpc8540ads/init.S index c495f1e..4c8dd0e 100644 --- a/board/freescale/mpc8540ads/init.S +++ b/board/freescale/mpc8540ads/init.S @@ -130,8 +130,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 1, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 2: 256M Non-cacheable, guarded @@ -139,8 +139,8 @@ tlb1_entry: */ .long FSL_BOOKE_MAS0(1, 2, 0) .long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) - .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_BASE + 0x10000000, (MAS2_I|MAS2_G)) - .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_BASE + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) + .long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G)) + .long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0, (MAS3_SX|MAS3_SW|MAS3_SR)) /* * TLB 3: 256M Non-cacheable, guarded diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c index ab6a6f2..785576a 100644 --- a/board/freescale/mpc8540ads/law.c +++ b/board/freescale/mpc8540ads/law.c @@ -48,7 +48,7 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), #endif - SET_LAW_ENTRY(2, CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), /* This is not so much the SDRAM map as it is the whole localbus map. */ SET_LAW_ENTRY(3, CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI), |