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| author | Kumar Gala <galak@kernel.crashing.org> | 2008-12-02 14:19:33 -0600 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2009-01-23 17:03:13 -0600 |
| commit | 52b565f5ad23b682489055b187767d8bf1c2e444 (patch) | |
| tree | f7e62f88a22deb0dcabe2b6c3ac85276d39cd907 /board/freescale/mpc8536ds | |
| parent | 30837e5b21d5a742983581ab9ee3fac085311d19 (diff) | |
| download | u-boot-imx-52b565f5ad23b682489055b187767d8bf1c2e444.zip u-boot-imx-52b565f5ad23b682489055b187767d8bf1c2e444.tar.gz u-boot-imx-52b565f5ad23b682489055b187767d8bf1c2e444.tar.bz2 | |
85xx: separate PIXIS virtual from physical address
Added a PIXIS_BASE_PHYS for use as the physical address and maintain
PIXIS_BASE as the virtual address of the PIXIS fpga registers.
This allows us to deal with 36-bit phys on these boards in the future.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/mpc8536ds')
| -rw-r--r-- | board/freescale/mpc8536ds/law.c | 2 | ||||
| -rw-r--r-- | board/freescale/mpc8536ds/tlb.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c index 0861fa7..caccce4 100644 --- a/board/freescale/mpc8536ds/law.c +++ b/board/freescale/mpc8536ds/law.c @@ -37,7 +37,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3), SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), - SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC), + SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c index c81a959..89d5097 100644 --- a/board/freescale/mpc8536ds/tlb.c +++ b/board/freescale/mpc8536ds/tlb.c @@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE, + SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_4K, 0), |