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| author | Kumar Gala <galak@kernel.crashing.org> | 2010-04-20 10:21:12 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-05-12 04:53:51 -0500 |
| commit | 54648985e2a64e29784e3ed37cd45b637305cd65 (patch) | |
| tree | ec82e7744e8f8738b2131add105dabb6a05978d1 /board/freescale/mpc8536ds/law.c | |
| parent | 6ab4011b796e0af130ca160ea3c674d462f3bec4 (diff) | |
| download | u-boot-imx-54648985e2a64e29784e3ed37cd45b637305cd65.zip u-boot-imx-54648985e2a64e29784e3ed37cd45b637305cd65.tar.gz u-boot-imx-54648985e2a64e29784e3ed37cd45b637305cd65.tar.bz2 | |
85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabled
The new is_serdes_configured covers a broader range of devices than the
PCI specific code. Use it instead as we convert away from the
is_fsl_pci_cfg() code.
Additionally move to setting LAWs for PCI based on if its configured.
Also updated PCI FDT fixup code to remove PCI controllers from dtb if
they are configured.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/mpc8536ds/law.c')
| -rw-r--r-- | board/freescale/mpc8536ds/law.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c index 1f11563..61b7454 100644 --- a/board/freescale/mpc8536ds/law.c +++ b/board/freescale/mpc8536ds/law.c @@ -28,15 +28,7 @@ #include <asm/mmu.h> struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), - SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2), - SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3), - SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3), SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), }; |