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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-10-16 15:01:15 +0200
committerWolfgang Denk <wd@denx.de>2008-10-18 21:54:03 +0200
commit6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch)
treeae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /board/freescale/m5282evb/m5282evb.c
parent71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff)
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rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/freescale/m5282evb/m5282evb.c')
-rw-r--r--board/freescale/m5282evb/m5282evb.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c
index 31d6923..b0c9fc8 100644
--- a/board/freescale/m5282evb/m5282evb.c
+++ b/board/freescale/m5282evb/m5282evb.c
@@ -36,7 +36,7 @@ phys_size_t initdram (int board_type)
{
u32 dramsize, i, dramclk;
- dramsize = CFG_SDRAM_SIZE * 0x100000;
+ dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
for (i = 0x13; i < 0x20; i++) {
if (dramsize == (1 << i))
break;
@@ -45,7 +45,7 @@ phys_size_t initdram (int board_type)
if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
{
- dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
+ dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
/* Initialize DRAM Control Register: DCR */
MCFSDRAMC_DCR = (0
@@ -55,7 +55,7 @@ phys_size_t initdram (int board_type)
/* Initialize DACR0 */
MCFSDRAMC_DACR0 = (0
- | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE)
+ | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
| MCFSDRAMC_DACR_CASL(1)
| MCFSDRAMC_DACR_CBM(3)
| MCFSDRAMC_DACR_PS_32);
@@ -77,7 +77,7 @@ phys_size_t initdram (int board_type)
}
/* Write to this block to initiate precharge */
- *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696;
+ *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
asm("nop");
/* Set RE (bit 15) in DACR */
@@ -94,7 +94,7 @@ phys_size_t initdram (int board_type)
asm("nop");
/* Write to the SDRAM Mode Register */
- *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
+ *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
}
return dramsize;
}