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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-10-16 15:01:15 +0200
committerWolfgang Denk <wd@denx.de>2008-10-18 21:54:03 +0200
commit6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch)
treeae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /board/freescale/m5271evb
parent71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff)
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rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/freescale/m5271evb')
-rw-r--r--board/freescale/m5271evb/m5271evb.c8
-rw-r--r--board/freescale/m5271evb/mii.c10
2 files changed, 9 insertions, 9 deletions
diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c
index e089d5f..5505cc4 100644
--- a/board/freescale/m5271evb/m5271evb.c
+++ b/board/freescale/m5271evb/m5271evb.c
@@ -66,7 +66,7 @@ phys_size_t initdram (int board_type) {
* PS: 32bit port size
*/
mbar_writeLong(MCF_SDRAMC_DACR0,
- MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
+ MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18)
| MCF_SDRAMC_DACRn_CASL(1)
| MCF_SDRAMC_DACRn_CBM(3)
| MCF_SDRAMC_DACRn_PS(0));
@@ -85,7 +85,7 @@ phys_size_t initdram (int board_type) {
asm(" nop");
/* Write to this block to initiate precharge */
- *(u32 *)(CFG_SDRAM_BASE) = 0xa5a5a5a5;
+ *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
/* Set RE bit in DACR */
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
@@ -108,10 +108,10 @@ phys_size_t initdram (int board_type) {
* Burst Type = Sequential
* Burst Length = 1
*/
- *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
+ *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
}
- return CFG_SDRAM_SIZE * 1024 * 1024;
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
int testdram (void) {
diff --git a/board/freescale/m5271evb/mii.c b/board/freescale/m5271evb/mii.c
index 78a7028..e79fa19 100644
--- a/board/freescale/m5271evb/mii.c
+++ b/board/freescale/m5271evb/mii.c
@@ -38,14 +38,14 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
{
if (setclear) {
/* Enable Ethernet pins */
- mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
+ mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
} else {
}
return 0;
}
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
#include <miiphy.h>
/* Make MII read/write commands for the FEC. */
@@ -131,9 +131,9 @@ uint mii_send(uint mii_cmd)
return (mii_reply & 0xffff); /* data read from phy */
}
-#endif /* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif /* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
{
#define MAX_PHY_PASSES 11
@@ -198,7 +198,7 @@ int mii_discover_phy(struct eth_device *dev)
return phyaddr;
}
-#endif /* CFG_DISCOVER_PHY */
+#endif /* CONFIG_SYS_DISCOVER_PHY */
void mii_init(void) __attribute__((weak,alias("__mii_init")));