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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-10-16 15:01:15 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:03 +0200 |
| commit | 6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch) | |
| tree | ae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /board/freescale/m5253evbe/m5253evbe.c | |
| parent | 71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff) | |
| download | u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.zip u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.gz u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.bz2 | |
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/freescale/m5253evbe/m5253evbe.c')
| -rw-r--r-- | board/freescale/m5253evbe/m5253evbe.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c index f3b1efd..ae69f67 100644 --- a/board/freescale/m5253evbe/m5253evbe.c +++ b/board/freescale/m5253evbe/m5253evbe.c @@ -43,7 +43,7 @@ phys_size_t initdram(int board_type) if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) { u32 RC, dramsize; - RC = (CFG_CLK / 1000000) >> 1; + RC = (CONFIG_SYS_CLK / 1000000) >> 1; RC = (RC * 15) >> 4; /* Initialize DRAM Control Register: DCR */ @@ -54,7 +54,7 @@ phys_size_t initdram(int board_type) asm("nop"); /* Initialize DMR0 */ - dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000; + dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000; mbar_writeLong(MCFSIM_DMR0, dramsize | 1); asm("nop"); @@ -62,7 +62,7 @@ phys_size_t initdram(int board_type) asm("nop"); /* Write to this block to initiate precharge */ - *(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5; + *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5; asm("nop"); /* Set RE bit in DACR */ @@ -78,10 +78,10 @@ phys_size_t initdram(int board_type) mbar_readLong(MCFSIM_DACR0) | 0x0040); asm("nop"); - *(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5; + *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5; } - return CFG_SDRAM_SIZE * 1024 * 1024; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; } int testdram(void) @@ -101,7 +101,7 @@ int ide_preinit(void) void ide_set_reset(int idereset) { - volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR; + volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; long period; /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */ int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */ @@ -118,7 +118,7 @@ void ide_set_reset(int idereset) mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND); #define CALC_TIMING(t) (t + period - 1) / period - period = 1000000000 / (CFG_CLK / 2); /* period in ns */ + period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ /*ata->ton = CALC_TIMING (180); */ ata->t1 = CALC_TIMING(piotms[2][0]); |