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| author | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
|---|---|---|
| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
| commit | cb5473205206c7f14cbb1e747f28ec75b48826e2 (patch) | |
| tree | 8f4808d60917100b18a10b05230f7638a0a9bbcc /board/freescale/m5235evb/m5235evb.c | |
| parent | baf449fc5ff96f071bb0e3789fd3265f6d4fd9a0 (diff) | |
| parent | 92c78a3bbcb2ce508b4bf1c4a1e0940406a024bb (diff) | |
| download | u-boot-imx-cb5473205206c7f14cbb1e747f28ec75b48826e2.zip u-boot-imx-cb5473205206c7f14cbb1e747f28ec75b48826e2.tar.gz u-boot-imx-cb5473205206c7f14cbb1e747f28ec75b48826e2.tar.bz2 | |
Merge branch 'fixes' into cleanups
Conflicts:
board/atmel/atngw100/atngw100.c
board/atmel/atstk1000/atstk1000.c
cpu/at32ap/at32ap700x/gpio.c
include/asm-avr32/arch-at32ap700x/clk.h
include/configs/atngw100.h
include/configs/atstk1002.h
include/configs/atstk1003.h
include/configs/atstk1004.h
include/configs/atstk1006.h
include/configs/favr-32-ezkit.h
include/configs/hammerhead.h
include/configs/mimc200.h
Diffstat (limited to 'board/freescale/m5235evb/m5235evb.c')
| -rw-r--r-- | board/freescale/m5235evb/m5235evb.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c index bd8a4e5..b9e6126 100644 --- a/board/freescale/m5235evb/m5235evb.c +++ b/board/freescale/m5235evb/m5235evb.c @@ -57,7 +57,7 @@ phys_size_t initdram(int board_type) GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3); - dramsize = CFG_SDRAM_SIZE * 0x100000; + dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000; for (i = 0x13; i < 0x20; i++) { if (dramsize == (1 << i)) break; @@ -65,7 +65,7 @@ phys_size_t initdram(int board_type) i--; if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) { - dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); + dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ); /* Initialize DRAM Control Register: DCR */ sdram->dcr = SDRAMC_DCR_RTIM_9CLKS | @@ -73,7 +73,7 @@ phys_size_t initdram(int board_type) /* Initialize DACR0 */ sdram->dacr0 = - SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 | + SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32; asm("nop"); @@ -90,7 +90,7 @@ phys_size_t initdram(int board_type) } /* Write to this block to initiate precharge */ - *(u32 *) (CFG_SDRAM_BASE) = 0xA5A59696; + *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696; /* Set RE (bit 15) in DACR */ sdram->dacr0 |= SDRAMC_DARCn_RE; @@ -105,7 +105,7 @@ phys_size_t initdram(int board_type) asm("nop"); /* Write to the SDRAM Mode Register */ - *(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696; + *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696; } return dramsize; |