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authorYork Sun <yorksun@freescale.com>2015-03-20 19:28:08 -0700
committerYork Sun <yorksun@freescale.com>2015-04-23 08:55:55 -0700
commit207774b213caa3c72ebd6c9f6d1e4a3a666938b7 (patch)
treeb0249e1f667a1c607cc1409dfbe7db7fb9b62840 /board/freescale/ls2085a/ls2085a.c
parent19f9175027b14f11b5a30df17ce76fb6f64dc724 (diff)
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armv8/ls2085a: Fix generic timer clock source
The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: York Sun <yorksun@freescale.com> CC: Mark Rutland <mark.rutland@arm.com>
Diffstat (limited to 'board/freescale/ls2085a/ls2085a.c')
-rw-r--r--board/freescale/ls2085a/ls2085a.c18
1 files changed, 0 insertions, 18 deletions
diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c
index e78c63a..bd016e9 100644
--- a/board/freescale/ls2085a/ls2085a.c
+++ b/board/freescale/ls2085a/ls2085a.c
@@ -55,24 +55,6 @@ int dram_init(void)
return 0;
}
-int timer_init(void)
-{
- u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
- u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
-
- /* Enable timebase for all clusters.
- * It is safe to do so even some clusters are not enabled.
- */
- out_le32(cltbenr, 0xf);
-
- /* Enable clock for timer
- * This is a global setting.
- */
- out_le32(cntcr, 0x1);
-
- return 0;
-}
-
/*
* Board specific reset that is system reset.
*/