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| author | Alison Wang <b18965@freescale.com> | 2014-12-09 17:38:02 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-12-11 09:40:14 -0800 |
| commit | d612f0ab34b27be4ad50b1236fbd6c84450997f1 (patch) | |
| tree | d175f1c357b997510468ebd220712f0a4a414c03 /board/freescale/ls1021atwr/ls1021atwr.c | |
| parent | 4c59ab9cfbdd34f5ef1e960470accdc63e2483c1 (diff) | |
| download | u-boot-imx-d612f0ab34b27be4ad50b1236fbd6c84450997f1.zip u-boot-imx-d612f0ab34b27be4ad50b1236fbd6c84450997f1.tar.gz u-boot-imx-d612f0ab34b27be4ad50b1236fbd6c84450997f1.tar.bz2 | |
arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/ls1021atwr/ls1021atwr.c')
| -rw-r--r-- | board/freescale/ls1021atwr/ls1021atwr.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 0faee0a..5c3a282 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -72,6 +72,7 @@ struct cpld_data { u8 rev2; /* Reserved */ }; +#ifndef CONFIG_QSPI_BOOT static void convert_serdes_mux(int type, int need_reset); void cpld_show(void) @@ -107,11 +108,14 @@ void cpld_show(void) in_8(&cpld_data->serdes_mux)); #endif } +#endif int checkboard(void) { puts("Board: LS1021ATWR\n"); +#ifndef CONFIG_QSPI_BOOT cpld_show(); +#endif return 0; } @@ -220,6 +224,7 @@ int board_eth_init(bd_t *bis) } #endif +#ifndef CONFIG_QSPI_BOOT int config_serdes_mux(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -251,6 +256,7 @@ int config_serdes_mux(void) return 0; } +#endif int board_early_init_f(void) { @@ -269,6 +275,10 @@ int board_early_init_f(void) out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); #endif +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + return 0; } @@ -305,8 +315,10 @@ int board_init(void) #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); +#ifndef CONFIG_QSPI_BOOT config_serdes_mux(); #endif +#endif #ifdef CONFIG_U_QE u_qe_init(); @@ -354,6 +366,7 @@ u16 flash_read16(void *addr) return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); } +#ifndef CONFIG_QSPI_BOOT static void convert_flash_bank(char bank) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); @@ -536,3 +549,4 @@ U_BOOT_CMD( " -change lane C & lane D to PCIeX2\n" "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" ); +#endif |