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| author | Alison Wang <b18965@freescale.com> | 2014-12-09 17:38:02 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-12-11 09:40:14 -0800 |
| commit | d612f0ab34b27be4ad50b1236fbd6c84450997f1 (patch) | |
| tree | d175f1c357b997510468ebd220712f0a4a414c03 /board/freescale/ls1021aqds/ls1021aqds.c | |
| parent | 4c59ab9cfbdd34f5ef1e960470accdc63e2483c1 (diff) | |
| download | u-boot-imx-d612f0ab34b27be4ad50b1236fbd6c84450997f1.zip u-boot-imx-d612f0ab34b27be4ad50b1236fbd6c84450997f1.tar.gz u-boot-imx-d612f0ab34b27be4ad50b1236fbd6c84450997f1.tar.bz2 | |
arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/ls1021aqds/ls1021aqds.c')
| -rw-r--r-- | board/freescale/ls1021aqds/ls1021aqds.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 9eab42d..9fcd129 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -34,7 +34,9 @@ enum { int checkboard(void) { +#ifndef CONFIG_QSPI_BOOT char buf[64]; +#endif #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) u8 sw; #endif @@ -61,12 +63,14 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif +#ifndef CONFIG_QSPI_BOOT printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); printf("FPGA: v%d (%s), build %d\n", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); +#endif return 0; } @@ -164,6 +168,10 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + /* Workaround for the issue that DDR could not respond to * barrier transaction which is generated by executing DSB/ISB * instruction. Set CCI-400 control override register to |