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authorFabio Estevam <fabio.estevam@freescale.com>2012-09-13 03:18:19 +0000
committerTom Rini <trini@ti.com>2012-10-15 11:54:08 -0700
commitaf7ec0b0582f658873713c311497626c571f3b31 (patch)
treefe8ab9d5ad6631fa4037e97fe3a360b81a601a69 /board/freescale/imx
parent539e9ffd92cef086d4b7d0a7efaabc294cd0b05a (diff)
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mx6q: Factor out common DDR3 init code
Factor out common DDR3 initialization code, allowing easier maintainance of such scripts. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'board/freescale/imx')
-rw-r--r--board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg170
1 files changed, 170 insertions, 0 deletions
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
new file mode 100644
index 0000000..62498ab
--- /dev/null
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -0,0 +1,170 @@
+# Copyright (C) 2011 Freescale Semiconductor, Inc.
+# Jason Liu <r64343@freescale.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# image version
+
+IMAGE_VERSION 2
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+
+BOOT_FROM sd
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type Address Value
+#
+# where:
+# Addr-type register length (1,2 or 4 bytes)
+# Address absolute address of the register
+# value value to be stored in the register
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+
+DATA 4 0x020e05ac 0x00020030
+DATA 4 0x020e05b4 0x00020030
+DATA 4 0x020e0528 0x00020030
+DATA 4 0x020e0520 0x00020030
+
+DATA 4 0x020e0514 0x00020030
+DATA 4 0x020e0510 0x00020030
+DATA 4 0x020e05bc 0x00020030
+DATA 4 0x020e05c4 0x00020030
+
+DATA 4 0x020e056c 0x00020030
+DATA 4 0x020e0578 0x00020030
+DATA 4 0x020e0588 0x00020030
+DATA 4 0x020e0594 0x00020030
+
+DATA 4 0x020e057c 0x00020030
+DATA 4 0x020e0590 0x00003000
+DATA 4 0x020e0598 0x00003000
+DATA 4 0x020e058c 0x00000000
+
+DATA 4 0x020e059c 0x00003030
+DATA 4 0x020e05a0 0x00003030
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0750 0x00020000
+
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0798 0x000C0000
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b0018 0x00081740
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b000c 0x555A7975
+DATA 4 0x021b0010 0xFF538E64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b002c 0x000026D2
+
+DATA 4 0x021b0030 0x005B0E21
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0040 0x00000027
+DATA 4 0x021b0000 0x831A0000
+
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x0408803A
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x0000803B
+DATA 4 0x021b001c 0x00428031
+DATA 4 0x021b001c 0x00428039
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x09408038
+
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b001c 0x04008048
+DATA 4 0x021b0800 0xA1380003
+DATA 4 0x021b4800 0xA1380003
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b4818 0x00022227
+
+DATA 4 0x021b083c 0x434B0350
+DATA 4 0x021b0840 0x034C0359
+DATA 4 0x021b483c 0x434B0350
+DATA 4 0x021b4840 0x03650348
+DATA 4 0x021b0848 0x4436383B
+DATA 4 0x021b4848 0x39393341
+DATA 4 0x021b0850 0x35373933
+DATA 4 0x021b4850 0x48254A36
+
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+
+DATA 4 0x021b480c 0x00440044
+DATA 4 0x021b4810 0x00440044
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b001c 0x00000000
+DATA 4 0x021b0404 0x00011006
+
+# set the default clock gate to save power
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+# enable AXI cache for VDOA/VPU/IPU
+DATA 4 0x020e0010 0xF00000CF
+# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F