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authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>2013-01-30 11:19:13 +0000
committerStefano Babic <sbabic@denx.de>2013-02-12 13:52:30 +0100
commit6904e377465db6c731adf4fb0eb67e55454606d7 (patch)
tree7dbec95763d0392f007717f316f20241774addf7 /board/freescale/imx/ddr
parent81ca840976e8e418ae8decaf03ea01f59b1b5be2 (diff)
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imx: mx6q DDR3 init: Fix tMRD
MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3. For all DDR3 speed bins: tMRD(min) = 4 nCK tMOD(min) = max(12 nCK, 15 ns) Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
Diffstat (limited to 'board/freescale/imx/ddr')
-rw-r--r--board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg2
1 files changed, 1 insertions, 1 deletions
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index c86cd40..9ac8027 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740
DATA 4 0x021b001c 0x00008000
DATA 4 0x021b000c 0x555A7975
-DATA 4 0x021b0010 0xFF538E64
+DATA 4 0x021b0010 0xFF538F64
DATA 4 0x021b0014 0x01FF00DB
DATA 4 0x021b002c 0x000026D2