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| author | York Sun <yorksun@freescale.com> | 2011-06-27 13:35:25 -0700 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2011-07-11 13:24:20 -0500 |
| commit | 4c99cb9190358e11ad96ba95b38d1e83cc053b46 (patch) | |
| tree | cccb23d6a1c90aaa2dc6aa8a654fae14345b8779 /board/freescale/corenet_ds/ddr.c | |
| parent | f2d264b6603239d6d214c4e2faf17dde64cf81e2 (diff) | |
| download | u-boot-imx-4c99cb9190358e11ad96ba95b38d1e83cc053b46.zip u-boot-imx-4c99cb9190358e11ad96ba95b38d1e83cc053b46.tar.gz u-boot-imx-4c99cb9190358e11ad96ba95b38d1e83cc053b46.tar.bz2 | |
powerpc/mpc8xxx: fix DDR data width checking
Checking width before setting DDR controller. SPD for DDR1 and DDR2 has
data width and primary sdram width. The latter one has different meaning
for DDR3.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'board/freescale/corenet_ds/ddr.c')
0 files changed, 0 insertions, 0 deletions