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authorWolfgang Denk <wd@denx.de>2011-11-16 20:06:21 +0100
committerWolfgang Denk <wd@denx.de>2011-11-16 20:06:21 +0100
commitc7801ee43b6263246e782000b71753caac5fe9c6 (patch)
tree1954eb9d5d051934839b70929f04603071335e18 /board/freescale/common
parent4055a6684781790ca29c8e25b858d55af173e145 (diff)
parent4589728e214958a4e6e011a081a68d360c49d7a5 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc8xxx/ddr/options.c: Fix GCC 4.6 build warning drivers/qe/uec.c: Fix GCC 4.6 build warning drivers/usb/host/ehci-fsl.c: Fix GCC 4.6 build warning drivers/net/fm/fm.c: Fix GCC 4.6 build warning board/sbc8560/sbc8560.c: Fix GCC 4.6 build warning board/sbc8548/sbc8548.c: Fix GCC 4.6 build warning board/freescale/mpc8569mds/mpc8569mds.c: Fix GCC 4.6 build warning board/freescale/mpc8568mds/mpc8568mds.c: Fix GCC 4.6 build warning board/freescale/mpc8548cds/mpc8548cds.c: Fix GCC 4.6 build warning board/freescale/common/pixis.c: Fix GCC 4.6 build warning board/freescale/common/cds_pci_ft.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc8xxx/fsl_lbc.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc85xx/tlb.c: Fix GCC 4.6 build warning arch/powerpc/cpu/mpc85xx/cpu_init.c: Fix GCC 4.6 build warning phylib: Enable AR8021 phy support powerpc/85xx: Set max alloc length to 10MB on P1022DS powerpc/mpc85xx: Set SYSCLK to the required frequency powerpc/85xx: Fix NAND SPL support powerpc/85xx: Fix MPC8572DS NAND build fsl_ifc: Fixed a bug in the erratum handling code for IFC_A003399 powerpc/85xx: Add support for Book-E MMU Arch v2.0 powerpc/85xx: Make inclusion of USB device fixup conditional powerpc/85xx: Fix warning for USB device-fixup powerpc/85xx: resize the boot page TLB before relocating CCSR powerpc/85xx: verify the current address of CCSR before relocating it powerpc/85xx: add some missing sync instructions in the CCSR relocation code powerpc/85xx: fix some comments in the CCSR relocation code powerpc/85xx: fix definition of MAS register macros powerpc/mpc8548cds: Fix network initialization powerpc/mpc8548: Add workaround for erratum NMG_eTSEC129 powerpc/QorIQ: fix network frame manager TBI PHY address settings
Diffstat (limited to 'board/freescale/common')
-rw-r--r--board/freescale/common/cds_pci_ft.c3
-rw-r--r--board/freescale/common/ics307_clk.c69
-rw-r--r--board/freescale/common/ics307_clk.h4
-rw-r--r--board/freescale/common/ngpixis.c27
-rw-r--r--board/freescale/common/pixis.c4
5 files changed, 101 insertions, 6 deletions
diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c
index 6f221af..8a09f99 100644
--- a/board/freescale/common/cds_pci_ft.c
+++ b/board/freescale/common/cds_pci_ft.c
@@ -28,13 +28,12 @@
#if defined(CONFIG_OF_BOARD_SETUP)
static void cds_pci_fixup(void *blob)
{
- int node, tmp[2];
+ int node;
const char *path;
int len, slot, i;
u32 *map = NULL;
node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
if (node >= 0) {
path = fdt_getprop(blob, node, "pci0", NULL);
if (path) {
diff --git a/board/freescale/common/ics307_clk.c b/board/freescale/common/ics307_clk.c
index 89d8810..6acbc36 100644
--- a/board/freescale/common/ics307_clk.c
+++ b/board/freescale/common/ics307_clk.c
@@ -31,12 +31,81 @@
#include "pixis.h"
#endif
+/* define for SYS CLK or CLK1Frequency */
+#define TTL 1
+#define CLK2 0
+#define CRYSTAL 0
+#define MAX_VDW (511 + 8)
+#define MAX_RDW (127 + 2)
+#define MIN_VDW (4 + 8)
+#define MIN_RDW (1 + 2)
+#define NUM_OD_SETTING 8
+/*
+ * These defines cover the industrial temperature range part,
+ * for commercial, change below to 400000 and 55000, respectively
+ */
+#define MAX_VCO 360000
+#define MIN_VCO 60000
+
/* decode S[0-2] to Output Divider (OD) */
static u8 ics307_s_to_od[] = {
10, 2, 8, 4, 5, 7, 3, 6
};
/*
+ * Find one solution to generate required frequency for SYSCLK
+ * out_freq: KHz, required frequency to the SYSCLK
+ * the result will be retuned with component RDW, VDW, OD, TTL,
+ * CLK2 and crystal
+ */
+unsigned long ics307_sysclk_calculator(unsigned long out_freq)
+{
+ const unsigned long input_freq = CONFIG_ICS307_REFCLK_HZ;
+ unsigned long vdw, rdw, odp, s_vdw = 0, s_rdw = 0, s_odp = 0, od;
+ unsigned long tmp_out, diff, result = 0;
+ int found = 0;
+
+ for (odp = 0; odp < NUM_OD_SETTING; odp++) {
+ od = ics307_s_to_od[odp];
+ if (od * out_freq < MIN_VCO || od * out_freq > MAX_VCO)
+ continue;
+ for (rdw = MIN_RDW; rdw <= MAX_RDW; rdw++) {
+ /* Calculate the VDW */
+ vdw = out_freq * 1000 * od * rdw / (input_freq * 2);
+ if (vdw > MAX_VDW)
+ vdw = MAX_VDW;
+ if (vdw < MIN_VDW)
+ continue;
+ /* Calculate the temp out frequency */
+ tmp_out = input_freq * 2 * vdw / (rdw * od * 1000);
+ diff = MAX(out_freq, tmp_out) - MIN(out_freq, tmp_out);
+ /*
+ * calculate the percent, the precision is 1/1000
+ * If greater than 1/1000, continue
+ * otherwise, we think the solution is we required
+ */
+ if (diff * 1000 / out_freq > 1)
+ continue;
+ else {
+ s_vdw = vdw;
+ s_rdw = rdw;
+ s_odp = odp;
+ found = 1;
+ break;
+ }
+ }
+ }
+
+ if (found)
+ result = (s_rdw - 2) | (s_vdw - 8) << 7 | s_odp << 16 |
+ CLK2 << 19 | TTL << 21 | CRYSTAL << 22;
+
+ debug("ICS307-02: RDW: %ld, VDW: %ld, OD: %d\n", s_rdw - 2, s_vdw - 8,
+ ics307_s_to_od[s_odp]);
+ return result;
+}
+
+/*
* Calculate frequency being generated by ICS307-02 clock chip based upon
* the control bytes being programmed into it.
*/
diff --git a/board/freescale/common/ics307_clk.h b/board/freescale/common/ics307_clk.h
index db3dbc4..3757912 100644
--- a/board/freescale/common/ics307_clk.h
+++ b/board/freescale/common/ics307_clk.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2010 Freescale Semiconductor, Inc.
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -23,8 +23,10 @@
#define __ICS_CLK_H_ 1
#ifndef __ASSEMBLY__
+
extern unsigned long get_board_sys_clk(void);
extern unsigned long get_board_ddr_clk(void);
+extern unsigned long ics307_sysclk_calculator(unsigned long out_freq);
#endif
#endif /* __ICS_CLK_H_ */
diff --git a/board/freescale/common/ngpixis.c b/board/freescale/common/ngpixis.c
index 765f035..276ae3c 100644
--- a/board/freescale/common/ngpixis.c
+++ b/board/freescale/common/ngpixis.c
@@ -156,9 +156,29 @@ static void pixis_dump_regs(void)
}
#endif
+void pixis_sysclk_set(unsigned long sysclk)
+{
+ unsigned long freq_word;
+ u8 sclk0, sclk1, sclk2;
+
+ freq_word = ics307_sysclk_calculator(sysclk);
+ sclk2 = freq_word & 0xff;
+ sclk1 = (freq_word >> 8) & 0xff;
+ sclk0 = (freq_word >> 16) & 0xff;
+
+ /* set SYSCLK enable bit */
+ PIXIS_WRITE(vcfgen0, 0x01);
+
+ /* SYSCLK to required frequency */
+ PIXIS_WRITE(sclk[0], sclk0);
+ PIXIS_WRITE(sclk[1], sclk1);
+ PIXIS_WRITE(sclk[2], sclk2);
+}
+
int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned int i;
+ unsigned long sysclk;
char *p_altbank = NULL;
#ifdef DEBUG
char *p_dump = NULL;
@@ -182,6 +202,12 @@ int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
continue;
}
#endif
+ if (strcmp(argv[i], "sysclk") == 0) {
+ sysclk = simple_strtoul(argv[i + 1], NULL, 0);
+ i += 1;
+ pixis_sysclk_set(sysclk);
+ continue;
+ }
unknown_param = argv[i];
}
@@ -219,4 +245,5 @@ U_BOOT_CMD(
#ifdef DEBUG
"pixis_reset dump - display the PIXIS registers\n"
#endif
+ "pixis_reset sysclk <SYSCLK_freq> - reset with SYSCLK frequency(KHz)\n"
);
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index a35b5cf..8d07061 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -380,7 +380,7 @@ static unsigned long strfractoint(char *strptr)
{
int i, j;
int mulconst;
- int intarr_len, no_dec = 0;
+ int no_dec = 0;
unsigned long intval = 0, decval = 0;
char intarr[3], decarr[3];
@@ -399,8 +399,6 @@ static unsigned long strfractoint(char *strptr)
i++;
}
- /* Assign length of integer part to intarr_len. */
- intarr_len = i;
intarr[i] = '\0';
if (no_dec) {