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author | Tang Yuantian <Yuantian.Tang@freescale.com> | 2014-11-21 11:17:15 +0800 |
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committer | York Sun <yorksun@freescale.com> | 2014-12-11 09:41:18 -0800 |
commit | a7787b78503a2c67fe02f1fcdd995fb6f3830f4b (patch) | |
tree | 26184f7b53fe7c7771f9de0a3505ece5054fa543 /board/freescale/common | |
parent | da5ce448c731321ba8cad5502a35c669b5e1bf8c (diff) | |
download | u-boot-imx-a7787b78503a2c67fe02f1fcdd995fb6f3830f4b.zip u-boot-imx-a7787b78503a2c67fe02f1fcdd995fb6f3830f4b.tar.gz u-boot-imx-a7787b78503a2c67fe02f1fcdd995fb6f3830f4b.tar.bz2 |
fsl/sleep: updated the deep sleep framework for QorIQ platforms
With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/common')
-rw-r--r-- | board/freescale/common/Makefile | 6 | ||||
-rw-r--r-- | board/freescale/common/arm_sleep.c | 95 | ||||
-rw-r--r-- | board/freescale/common/mpc85xx_sleep.c | 88 | ||||
-rw-r--r-- | board/freescale/common/sleep.h | 21 |
4 files changed, 210 insertions, 0 deletions
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 59ddeef..9a91b90 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -37,6 +37,12 @@ endif obj-$(CONFIG_FSL_DIU_CH7301) += diu_ch7301.o +ifdef CONFIG_ARM +obj-$(CONFIG_DEEP_SLEEP) += arm_sleep.o +else +obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o +endif + obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c new file mode 100644 index 0000000..8edf878 --- /dev/null +++ b/board/freescale/common/arm_sleep.c @@ -0,0 +1,95 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT) +#error " Deep sleep needs non-secure mode support. " +#else +#include <asm/secure.h> +#endif +#include <asm/armv7.h> +#include <asm/cache.h> + +#if defined(CONFIG_LS102XA) +#include <asm/arch/immap_ls102xa.h> +#endif + +#include "sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +void __weak board_mem_sleep_setup(void) +{ +} + +void __weak board_sleep_prepare(void) +{ +} + +bool is_warm_boot(void) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} + +void fsl_dp_disable_console(void) +{ + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +} + +/* + * When wakeup from deep sleep, the first 128 bytes space + * will be used to do DDR training which corrupts the data + * in there. This function will restore them. + */ +static void dp_ddr_restore(void) +{ + u64 *src, *dst; + int i; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + + /* get the address of ddr date from SPARECR3 */ + src = (u64 *)in_le32(&scfg->sparecr[2]); + dst = (u64 *)CONFIG_SYS_SDRAM_BASE; + + for (i = 0; i < DDR_BUFF_LEN / 8; i++) + *dst++ = *src++; + + flush_dcache_all(); +} + +static void dp_resume_prepare(void) +{ + dp_ddr_restore(); + board_sleep_prepare(); + armv7_init_nonsec(); + cleanup_before_linux(); +} + +int fsl_dp_resume(void) +{ + u32 start_addr; + void (*kernel_resume)(void); + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + + if (!is_warm_boot()) + return 0; + + dp_resume_prepare(); + + /* Get the entry address and jump to kernel */ + start_addr = in_le32(&scfg->sparecr[1]); + debug("Entry address is 0x%08x\n", start_addr); + kernel_resume = (void (*)(void))start_addr; + secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0); + + return 0; +} diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c new file mode 100644 index 0000000..f924e7f --- /dev/null +++ b/board/freescale/common/mpc85xx_sleep.c @@ -0,0 +1,88 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/immap_85xx.h> +#include "sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +void __weak board_mem_sleep_setup(void) +{ +} + +void __weak board_sleep_prepare(void) +{ +} + +bool is_warm_boot(void) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} + +void fsl_dp_disable_console(void) +{ + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +} + +/* + * When wakeup from deep sleep, the first 128 bytes space + * will be used to do DDR training which corrupts the data + * in there. This function will restore them. + */ +static void dp_ddr_restore(void) +{ + volatile u64 *src, *dst; + int i; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; + + /* get the address of ddr date from SPARECR3 */ + src = (u64 *)in_be32(&scfg->sparecr[2]); + dst = (u64 *)CONFIG_SYS_SDRAM_BASE; + + for (i = 0; i < DDR_BUFF_LEN / 8; i++) + *dst++ = *src++; + + flush_dcache(); +} + +static void dp_resume_prepare(void) +{ + dp_ddr_restore(); + + board_sleep_prepare(); + + l2cache_init(); +#if defined(CONFIG_RAMBOOT_PBL) + disable_cpc_sram(); +#endif + enable_cpc(); +} + +int fsl_dp_resume(void) +{ + u32 start_addr; + void (*kernel_resume)(void); + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; + + if (!is_warm_boot()) + return 0; + + dp_resume_prepare(); + + /* Get the entry address and jump to kernel */ + start_addr = in_be32(&scfg->sparecr[1]); + debug("Entry address is 0x%08x\n", start_addr); + kernel_resume = (void (*)(void))start_addr; + kernel_resume(); + + return 0; +} diff --git a/board/freescale/common/sleep.h b/board/freescale/common/sleep.h new file mode 100644 index 0000000..c26c542 --- /dev/null +++ b/board/freescale/common/sleep.h @@ -0,0 +1,21 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SLEEP_H +#define __SLEEP_H + +#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) +#define DDR_BUFF_LEN 128 + +/* determine if it is a wakeup from deep sleep */ +bool is_warm_boot(void); + +/* disable console output */ +void fsl_dp_disable_console(void); + +/* clean up everything and jump to kernel */ +int fsl_dp_resume(void); +#endif |