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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2013-09-24 15:58:35 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-10-16 16:15:17 -0700 |
| commit | 787964b8118b47a50bda796a315068639977c884 (patch) | |
| tree | 65acee6e6a40cf39e8d19e4c499ca05c3f91be3f /board/freescale/c29xpcie | |
| parent | 133fbfa9e6a81a59ab2d6848f0b111ebb2567a8a (diff) | |
| download | u-boot-imx-787964b8118b47a50bda796a315068639977c884.zip u-boot-imx-787964b8118b47a50bda796a315068639977c884.tar.gz u-boot-imx-787964b8118b47a50bda796a315068639977c884.tar.bz2 | |
boards/c29xpcie: Update TLB and LAW size for IFC NAND, CPLD
NAND,CPLD AMASK register is programmed for 64K size.
so Update TLB & LAW size accordingly.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Diffstat (limited to 'board/freescale/c29xpcie')
| -rw-r--r-- | board/freescale/c29xpcie/law.c | 4 | ||||
| -rw-r--r-- | board/freescale/c29xpcie/tlb.c | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c index cd8fc21..80e5fff 100644 --- a/board/freescale/c29xpcie/law.c +++ b/board/freescale/c29xpcie/law.c @@ -10,8 +10,8 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_16K, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K, LAW_TRGT_IF_PLATFORM_SRAM), }; diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c index ddd1ef8..84844ee 100644 --- a/board/freescale/c29xpcie/tlb.c +++ b/board/freescale/c29xpcie/tlb.c @@ -46,11 +46,11 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_4K, 1), + 0, 4, BOOKE_PAGESZ_64K, 1), SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_16K, 1), + 0, 5, BOOKE_PAGESZ_64K, 1), SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, |