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| author | Po Liu <po.liu@freescale.com> | 2013-09-26 09:40:11 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-10-24 09:34:56 -0700 |
| commit | 9c25ee6d3a63d450a89ed5bb35002210a91699a2 (patch) | |
| tree | cc7ad8f160028942f6a56c2b04909e971c5a77af /board/freescale/c29xpcie | |
| parent | 7e575c46c34b5f1316eab39025fdced197629ccb (diff) | |
| download | u-boot-imx-9c25ee6d3a63d450a89ed5bb35002210a91699a2.zip u-boot-imx-9c25ee6d3a63d450a89ed5bb35002210a91699a2.tar.gz u-boot-imx-9c25ee6d3a63d450a89ed5bb35002210a91699a2.tar.bz2 | |
powerpc/c29xpcie: add DDR ECC on off config setting
c29xpcie REV_A board DDR ECC chip has bad impedance in hardware,
force that kind of board to be DDR ECC off when booting.
Other version board config ECC on/off by hwconfig=fsl_ddr:ecc=on
in uboot enviroment.
Signed-off-by: Po Liu <Po.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/c29xpcie')
| -rw-r--r-- | board/freescale/c29xpcie/ddr.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c index 804ea19..57a9b61 100644 --- a/board/freescale/c29xpcie/ddr.c +++ b/board/freescale/c29xpcie/ddr.c @@ -9,6 +9,9 @@ #include <asm/fsl_ddr_sdram.h> #include <asm/fsl_ddr_dimm_params.h> +#include "cpld.h" + +#define C29XPCIE_HARDWARE_REVA 0x40 /* * Micron MT41J128M16HA-15E * */ @@ -61,7 +64,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) { + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); int i; + popts->clk_adjust = 4; popts->cpo_override = 0x1f; popts->write_data_delay = 4; @@ -79,6 +84,9 @@ void fsl_ddr_board_options(memctl_options_t *popts, popts->trwt_override = 1; popts->trwt = 0; + if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA) + popts->ecc_mode = 0; + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; |