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| author | York Sun <yorksun@freescale.com> | 2013-06-03 12:39:06 -0700 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-11-25 11:43:46 -0800 |
| commit | d4263b8adb5bd940c95cbaebaa0da9eaf759bfed (patch) | |
| tree | 730993df736380d8b77fb4128fd6a0e3f4c0b663 /board/freescale/c29xpcie/c29xpcie.c | |
| parent | 9ac4ffbde1a5015c9929ee8578d3811b716e2fd3 (diff) | |
| download | u-boot-imx-d4263b8adb5bd940c95cbaebaa0da9eaf759bfed.zip u-boot-imx-d4263b8adb5bd940c95cbaebaa0da9eaf759bfed.tar.gz u-boot-imx-d4263b8adb5bd940c95cbaebaa0da9eaf759bfed.tar.bz2 | |
powerpc/mpc8xxx: Extend DDR registers' fields
Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR controllers. Writing to those fields are safely ignored.
TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE
automatically. It was a misunderstanding in commit c360ceac.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/c29xpcie/c29xpcie.c')
0 files changed, 0 insertions, 0 deletions