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| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2013-07-02 09:21:04 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2013-08-09 12:41:40 -0700 |
| commit | 64501c669851e45dd47699349dae6b5798c075a3 (patch) | |
| tree | 9ac713a2c30d740ea29a0888d9ca357b89db1ed3 /board/freescale/bsc9132qds/law.c | |
| parent | 17b8614754e9adc531d3f1bc3db66bf680a09447 (diff) | |
| download | u-boot-imx-64501c669851e45dd47699349dae6b5798c075a3.zip u-boot-imx-64501c669851e45dd47699349dae6b5798c075a3.tar.gz u-boot-imx-64501c669851e45dd47699349dae6b5798c075a3.tar.bz2 | |
board/bsc9132qds: Add DSP side tlb and laws
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a
integrated device that contains two powerpc e500v2 cores and two DSP
starcores.
To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 and M3 memory
-Creating LAW for 1GB DDR which is connected exclusively to DSP-cores
Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/bsc9132qds/law.c')
| -rw-r--r-- | board/freescale/bsc9132qds/law.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c index fed2edf..e10de9a 100644 --- a/board/freescale/bsc9132qds/law.c +++ b/board/freescale/bsc9132qds/law.c @@ -16,6 +16,14 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_FPGA_BASE_PHYS SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), #endif + SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M, + LAW_TRGT_IF_DSP_CCSR), + SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M, + LAW_TRGT_IF_OCN_DSP), + SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K, + LAW_TRGT_IF_CLASS_DSP), + SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G, + LAW_TRGT_IF_CLASS_DSP) }; int num_law_entries = ARRAY_SIZE(law_table); |