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| author | Priyanka Jain <Priyanka.Jain@freescale.com> | 2013-04-04 09:31:54 +0530 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-06-20 16:09:08 -0500 |
| commit | 765b0bdb899d614d0455f19548901b79f2baa66c (patch) | |
| tree | 7508adf27d2e7f7ae32c925ba555f33528a1b1e8 /board/freescale/bsc9131rdb/tlb.c | |
| parent | 087cf44fcd237d965ecccd6cf9e52de8d3c51a2e (diff) | |
| download | u-boot-imx-765b0bdb899d614d0455f19548901b79f2baa66c.zip u-boot-imx-765b0bdb899d614d0455f19548901b79f2baa66c.tar.gz u-boot-imx-765b0bdb899d614d0455f19548901b79f2baa66c.tar.bz2 | |
board/bsc9131rdb: Add DSP side tlb and laws
BSC9131RDB is a Freescale Reference Design Board for
BSC9131 SoC which is a integrated device that contains
one powerpc e500v2 core and one DSP starcore.
To support DSP starcore
-Creating LAW and TLB for DSP-CCSR space.
-Creating LAW for DSP-core subsystem M2 memory
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/freescale/bsc9131rdb/tlb.c')
| -rw-r--r-- | board/freescale/bsc9131rdb/tlb.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c index 243a38f..8a7c0ec 100644 --- a/board/freescale/bsc9131rdb/tlb.c +++ b/board/freescale/bsc9131rdb/tlb.c @@ -52,6 +52,12 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), + /* CCSRBAR (DSP) */ + SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, + CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_1M, 1), + #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, |