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authorPrabhakar Kushwaha <prabhakar@freescale.com>2014-04-08 19:13:44 +0530
committerYork Sun <yorksun@freescale.com>2014-04-22 17:58:51 -0700
commitc5dfe6ec58e0b504cba5b429200f6a5d217d5bd9 (patch)
treeb769cf573080fcd60892b9bb49e3abaab76bc436 /board/freescale/b4860qds/ddr.c
parent89ad7be8e713f33ec677cf4576e0c9b0ed83f7c6 (diff)
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board/b4qds:Add support of 2 stage NAND boot-loader
Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board/freescale/b4860qds/ddr.c')
-rw-r--r--board/freescale/b4860qds/ddr.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index 187c3b3..2c17156 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -179,6 +179,7 @@ phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
@@ -186,7 +187,9 @@ phys_size_t initdram(int board_type)
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
- puts(" DDR: ");
+#else
+ dram_size = fsl_ddr_sdram_size();
+#endif
return dram_size;
}