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| author | Stefan Roese <sr@denx.de> | 2008-10-21 11:43:08 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-10-21 11:43:08 +0200 |
| commit | f61f1e150c84f5b9347fca79a4bc5f2286c545d2 (patch) | |
| tree | ab90f076f18e56b2b3e8c9375b95917daa78c1d9 /board/flagadm/flagadm.c | |
| parent | ec081c2c190148b374e86a795fb6b1c49caeb549 (diff) | |
| parent | f82642e33899766892499b163e60560fbbf87773 (diff) | |
| download | u-boot-imx-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.zip u-boot-imx-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.tar.gz u-boot-imx-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.tar.bz2 | |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'board/flagadm/flagadm.c')
| -rw-r--r-- | board/flagadm/flagadm.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/board/flagadm/flagadm.c b/board/flagadm/flagadm.c index 7caedc9..dc9e2dc 100644 --- a/board/flagadm/flagadm.c +++ b/board/flagadm/flagadm.c @@ -98,18 +98,18 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0; - memctl->memc_or2 = CFG_OR2; - memctl->memc_br2 = CFG_BR2; + memctl->memc_or2 = CONFIG_SYS_OR2; + memctl->memc_br2 = CONFIG_SYS_BR2; udelay(100); upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); memctl->memc_mptpr = MPTPR_PTP_DIV16; - memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_1X; + memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_1X; /*Do the initialization of the SDRAM*/ /*Start with the precharge cycle*/ @@ -117,7 +117,7 @@ phys_size_t initdram (int board_type) MCR_MLCF(1) | MCR_MAD(0x5)); /*Then we need two refresh cycles*/ - memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_2X; + memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_2X; memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \ MCR_MLCF(2) | MCR_MAD(0x30)); @@ -127,7 +127,7 @@ phys_size_t initdram (int board_type) MCR_MLCF(1) | MCR_MAD(0x1C)); /* That should do it, just enable the periodic refresh in burst of 4*/ - memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_4X; + memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_4X; memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS); size_b0 = 16*1024*1024; @@ -143,8 +143,8 @@ phys_size_t initdram (int board_type) memctl->memc_mbmr = MBMR_GPL_B4DIS; - memctl->memc_or4 = CFG_OR4; - memctl->memc_br4 = CFG_BR4; + memctl->memc_or4 = CONFIG_SYS_OR4; + memctl->memc_br4 = CONFIG_SYS_BR4; return (size_b0); } |