mpc85xx: Add board support for the eXMeritus HWW-1U-1A devices

The eXMeritus HWW-1U-1A unit is a DO-160-certified 13lb 1U chassis
with 3 independent TEMPEST zones.  Two independent P2020 computers may
be found inside each zone.  Complete hardware support is included.

High-level hardware overview:
  * DO-160 certified for passenger aircraft (noncritical)
  * TEMPEST ceritified for RED/BLACK separation
  * 3 zones per chassis, 2 computers per zone (total of 6)
  * Dual-core 1.066GHz P2020 per computer
  * One 2GB DDR2 SO-RDIMM module per computer (upgradable to 4GB)
  * Removable 80GB or 160GB Intel X18-M SSD per computer
  * Front-accessible dual-port E1000E per computer
  * Front-accessible serial console per computer
  * Front-accessible USB port per computer
  * Internal Gigabit crossover within each TEMPEST zone
  * Internal unidirectional fiber links across TEMPEST zones
  * Battery-backed DS1339 I2C RTC on each CPU.

Combined, each 13lb 1U chassis contains 12GB RAM, 12 cores @ 1.066GHz,
12 front-accessible Gigabit Ethernet ports and 960GB of solid-state
storage with a total power consumption of ~200W.

Additional notes:
  * SPD detection is only known to work with the DO-160-certified DIMMs

  * CPU reset is a little quirky due to hardware misfeature.  Proper
    support for the hardware reset mechanism has been left for a later
    patch series to address.

Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 106 insertions, 0 deletions

diff --git a/board/exmeritus/hww1u1a/tlb.c b/board/exmeritus/hww1u1a/tlb.c
new file mode 100644
index 0000000..6c65206
--- /dev/null
+++ b/board/exmeritus/hww1u1a/tlb.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2009-2010 eXMeritus, A Boeing Company
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      +  0 * 1024,
+				CONFIG_SYS_INIT_RAM_ADDR_PHYS +  0 * 1024,
+				MAS3_SX|MAS3_SW|MAS3_SR, 0,
+				0, 0, BOOKE_PAGESZ_4K, 0),
+
+	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      +  4 * 1024,
+				CONFIG_SYS_INIT_RAM_ADDR_PHYS +  4 * 1024,
+				MAS3_SX|MAS3_SW|MAS3_SR, 0,
+				0, 0, BOOKE_PAGESZ_4K, 0),
+
+	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      +  8 * 1024,
+				CONFIG_SYS_INIT_RAM_ADDR_PHYS +  8 * 1024,
+				MAS3_SX|MAS3_SW|MAS3_SR, 0,
+				0, 0, BOOKE_PAGESZ_4K, 0),
+
+	SET_TLB_ENTRY(0,	CONFIG_SYS_INIT_RAM_ADDR      + 12 * 1024,
+				CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+				MAS3_SX|MAS3_SW|MAS3_SR, 0,
+				0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Boot page */
+	SET_TLB_ENTRY(1,	CONFIG_BPTR_VIRT_ADDR,
+				CONFIG_BPTR_VIRT_ADDR,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1,	CONFIG_SYS_CCSRBAR,
+				CONFIG_SYS_CCSRBAR_PHYS,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/*
+	 * W**G* - FLASH (Will be *I*G* after relocation to RAM)
+	 *
+	 * This maps both SPI FLASH chips (128MByte per chip)
+	 */
+	SET_TLB_ENTRY(1,	CONFIG_SYS_FLASH_BASE,
+				CONFIG_SYS_FLASH_BASE_PHYS,
+				MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+				0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * *I*G* - PCI memory
+	 *
+	 * We have 1.5GB total PCI-E memory space to map and we want to use
+	 * the minimum possible number of TLB entries.  Since Book-E TLB
+	 * entries are sized in powers of 4, we use 1GB + 256MB + 256MB.
+	 */
+	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_MEM_VIRT,
+				CONFIG_SYS_PCIE3_MEM_PHYS,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 3, BOOKE_PAGESZ_1G, 1),
+	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+				CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 4, BOOKE_PAGESZ_256M, 1),
+	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+				CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * *I*G* - PCI I/O
+	 *
+	 * This one entry covers all 3 64k PCI-E I/O windows
+	 */
+	SET_TLB_ENTRY(1,	CONFIG_SYS_PCIE3_IO_VIRT,
+				CONFIG_SYS_PCIE3_IO_PHYS,
+				MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+				0, 6, BOOKE_PAGESZ_256K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);