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authorHaavard Skinnemoen <haavard.skinnemoen@atmel.com>2008-12-17 16:53:07 +0100
committerHaavard Skinnemoen <haavard.skinnemoen@atmel.com>2008-12-17 16:53:07 +0100
commitcb5473205206c7f14cbb1e747f28ec75b48826e2 (patch)
tree8f4808d60917100b18a10b05230f7638a0a9bbcc /board/etin/kvme080/kvme080.c
parentbaf449fc5ff96f071bb0e3789fd3265f6d4fd9a0 (diff)
parent92c78a3bbcb2ce508b4bf1c4a1e0940406a024bb (diff)
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Merge branch 'fixes' into cleanups
Conflicts: board/atmel/atngw100/atngw100.c board/atmel/atstk1000/atstk1000.c cpu/at32ap/at32ap700x/gpio.c include/asm-avr32/arch-at32ap700x/clk.h include/configs/atngw100.h include/configs/atstk1002.h include/configs/atstk1003.h include/configs/atstk1004.h include/configs/atstk1006.h include/configs/favr-32-ezkit.h include/configs/hammerhead.h include/configs/mimc200.h
Diffstat (limited to 'board/etin/kvme080/kvme080.c')
-rw-r--r--board/etin/kvme080/kvme080.c36
1 files changed, 21 insertions, 15 deletions
diff --git a/board/etin/kvme080/kvme080.c b/board/etin/kvme080/kvme080.c
index bfd6854..8c6afc9 100644
--- a/board/etin/kvme080/kvme080.c
+++ b/board/etin/kvme080/kvme080.c
@@ -25,6 +25,7 @@
#include <mpc824x.h>
#include <pci.h>
#include <i2c.h>
+#include <netdev.h>
#include <asm/processor.h>
int checkboard(void)
@@ -45,7 +46,7 @@ unsigned long setdram(int m, int row, int col, int bank)
CONFIG_READ_WORD(MCCR1, mccr1);
mccr1 &= 0xffff0000;
- start = CFG_SDRAM_BASE;
+ start = CONFIG_SYS_SDRAM_BASE;
end = start + (1 << (col + row + 3) ) * bank - 1;
for (i = 0; i < m; i++) {
@@ -100,31 +101,31 @@ phys_size_t initdram(int board_type)
msr = mfmsr();
mtmsr(msr & ~(MSR_IR | MSR_DR));
- mtspr(IBAT2L, CFG_IBAT0L + 0x10000000);
- mtspr(IBAT2U, CFG_IBAT0U + 0x10000000);
- mtspr(DBAT2L, CFG_DBAT0L + 0x10000000);
- mtspr(DBAT2U, CFG_DBAT0U + 0x10000000);
+ mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
+ mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
+ mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
+ mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
mtmsr(msr);
- if (setdram(2,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x20000000))
+ if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
size = 0x20000000; /* 512MB */
- else if (setdram(1,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
+ else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
size = 0x10000000; /* 256MB */
- else if (setdram(2,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
+ else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
size = 0x10000000; /* 256MB */
- else if (setdram(1,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
+ else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
size = 0x08000000; /* 128MB */
- else if (setdram(2,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
+ else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
size = 0x08000000; /* 128MB */
- else if (setdram(1,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x04000000))
+ else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
size = 0x04000000; /* 64MB */
msr = mfmsr();
mtmsr(msr & ~(MSR_IR | MSR_DR));
- mtspr(IBAT2L, CFG_IBAT2L);
- mtspr(IBAT2U, CFG_IBAT2U);
- mtspr(DBAT2L, CFG_DBAT2L);
- mtspr(DBAT2U, CFG_DBAT2U);
+ mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
+ mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
+ mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
+ mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
mtmsr(msr);
return size;
@@ -191,3 +192,8 @@ void nvram_write(long dest, const void *src, size_t count)
asm volatile("sync");
}
}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}