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| author | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:59:44 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:59:44 +0200 |
| commit | f82642e33899766892499b163e60560fbbf87773 (patch) | |
| tree | ab90f076f18e56b2b3e8c9375b95917daa78c1d9 /board/esteem192e/esteem192e.c | |
| parent | b59b16ca24bc7e77ec113021a6d77b9b32fcf192 (diff) | |
| parent | 360fe71e82b83e264c964c9447c537e9a1f643c8 (diff) | |
| download | u-boot-imx-f82642e33899766892499b163e60560fbbf87773.zip u-boot-imx-f82642e33899766892499b163e60560fbbf87773.tar.gz u-boot-imx-f82642e33899766892499b163e60560fbbf87773.tar.bz2 | |
Merge 'next' branch
Conflicts:
board/freescale/mpc8536ds/mpc8536ds.c
include/configs/mgcoge.h
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'board/esteem192e/esteem192e.c')
| -rw-r--r-- | board/esteem192e/esteem192e.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/board/esteem192e/esteem192e.c b/board/esteem192e/esteem192e.c index f3c8662..b784cbb 100644 --- a/board/esteem192e/esteem192e.c +++ b/board/esteem192e/esteem192e.c @@ -103,7 +103,7 @@ int checkboard (void) phys_size_t initdram (int board_type) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; long int size_b0, size_b1; @@ -113,7 +113,7 @@ phys_size_t initdram (int board_type) memctl->memc_mptpr = 0x0200; /* divide by 32 */ - memctl->memc_mamr = 0x18003112; /*CFG_MAMR_8COL; */ /* 0x18005112 TODO: explain here */ + memctl->memc_mamr = 0x18003112; /*CONFIG_SYS_MAMR_8COL; */ /* 0x18005112 TODO: explain here */ upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); @@ -124,11 +124,11 @@ phys_size_t initdram (int board_type) * SDRAM size has been determined. */ - memctl->memc_or2 = CFG_OR2_PRELIM; /* not defined yet */ - memctl->memc_br2 = CFG_BR2_PRELIM; + memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; /* not defined yet */ + memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; - memctl->memc_or3 = CFG_OR3_PRELIM; - memctl->memc_br3 = CFG_BR3_PRELIM; + memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM; + memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM; /* perform SDRAM initializsation sequence */ @@ -139,7 +139,7 @@ phys_size_t initdram (int board_type) memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */ memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */ - memctl->memc_mamr = CFG_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */ + memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */ /* printf ("banks 0 and 1 are programed\n"); */ |