diff options
| author | Wolfgang Denk <wd@denx.de> | 2009-06-14 22:05:42 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-06-14 22:05:42 +0200 |
| commit | 92afd368bba7d98b2b7bfb51082c3639bb2119b3 (patch) | |
| tree | 74ffc8a3f4980f7c6bad6bf80bb41d3974eff685 /board/esd | |
| parent | 6b1f78ae6ad037382ad430b07064105c88f7ac02 (diff) | |
| parent | 388517e4b745b00256c2fa201ce7bccb67b4f245 (diff) | |
| download | u-boot-imx-92afd368bba7d98b2b7bfb51082c3639bb2119b3.zip u-boot-imx-92afd368bba7d98b2b7bfb51082c3639bb2119b3.tar.gz u-boot-imx-92afd368bba7d98b2b7bfb51082c3639bb2119b3.tar.bz2 | |
Merge branch 'next' of ../master
Diffstat (limited to 'board/esd')
38 files changed, 757 insertions, 8097 deletions
diff --git a/board/esd/ar405/ar405.c b/board/esd/ar405/ar405.c index 14520e1..9d1b6d2 100644 --- a/board/esd/ar405/ar405.c +++ b/board/esd/ar405/ar405.c @@ -247,9 +247,8 @@ int do_digtest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( digtest, 3, 1, do_digtest, "Test digital in-/output", - NULL - ); - + "" +); #define ERROR_DELTA 256 @@ -341,8 +340,8 @@ int do_anatest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( anatest, 2, 1, do_anatest, "Test analog in-/output", - NULL - ); + "" +); int counter = 0; @@ -408,6 +407,6 @@ int do_inctest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( inctest, 3, 1, do_inctest, "Test incremental encoder inputs", - NULL - ); + "" +); #endif diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index 9a522b2..01b1223 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -31,14 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; extern void lxt971_no_sleep(void); -/* fpga configuration data - not compressed, generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; -int filesize = sizeof(fpgadata); - - int board_early_init_f (void) { /* @@ -197,8 +189,9 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - NULL); + "Enable / disable / query EEPROM write access", + "" +); #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ /* ------------------------------------------------------------------------- */ diff --git a/board/esd/cms700/config.mk b/board/esd/cms700/config.mk index 5c3c01c..8e48bcd 100644 --- a/board/esd/cms700/config.mk +++ b/board/esd/cms700/config.mk @@ -20,9 +20,4 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - -# -# esd CMS405 boards -# - -TEXT_BASE = 0xFFFC0000 +TEXT_BASE = 0xFFFC8000 diff --git a/board/esd/cms700/fpgadata.c b/board/esd/cms700/fpgadata.c deleted file mode 100644 index 08be5e7..0000000 --- a/board/esd/cms700/fpgadata.c +++ /dev/null @@ -1,1812 +0,0 @@ - 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0x00,0x35,0xd0,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00, - 0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0xd0,0x00,0x00,0x00,0x01,0x00,0x00, - 0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x04,0x00,0x00, - 0x00,0x64,0x02,0x08,0xf0,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,0xff, - 0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00,0x00,0x00, diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index 8593125..33aeb46 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -551,6 +551,6 @@ int auto_update(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( autoupd, 1, 1, auto_update, "Automatically update images", - NULL + "" ); #endif /* CONFIG_AUTO_UPDATE */ diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c index c779f79..47e946f 100644 --- a/board/esd/common/cmd_loadpci.c +++ b/board/esd/common/cmd_loadpci.c @@ -124,7 +124,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( loadpci, 1, 1, do_loadpci, "Wait for pci bootcmd and boot it", - NULL - ); + "" +); #endif diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c index 066df74..5c50b4c 100644 --- a/board/esd/common/lcd.c +++ b/board/esd/common/lcd.c @@ -373,5 +373,5 @@ int do_esdbmp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( esdbmp, 2, 1, do_esdbmp, "display BMP image", - "<imageAddr> - display image\n" + "<imageAddr> - display image" ); diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c index 9b2cf90..414e821 100644 --- a/board/esd/common/xilinx_jtag/micro.c +++ b/board/esd/common/xilinx_jtag/micro.c @@ -66,10 +66,7 @@ #include "lenval.h" #include "ports.h" - -extern const unsigned char fpgadata[]; -extern int filesize; - +const unsigned char *xsvfdata; /*============================================================================ * XSVF #define @@ -1838,12 +1835,23 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) unsigned long duration; unsigned long long startClock, endClock; + if (argc == 2) + xsvfdata = (unsigned char *)simple_strtoul(argv[1], NULL, 16); + else { +#ifdef CONFIG_SYS_XSVF_DEFAULT_ADDR + xsvfdata = (unsigned char *)CONFIG_SYS_XSVF_DEFAULT_ADDR; +#else + printf("Usage:\ncpld %s\n", cmdtp->help); + return -1; +#endif + } + iErrorCode = XSVF_ERRORCODE( XSVF_ERROR_NONE ); pzXsvfFileName = 0; xsvf_iDebugLevel = 0; printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION); - printf("XSVF Filesize = %d bytes\n", filesize); + printf("Reading XSVF data @ %p\n", xsvfdata); /* Initialize the I/O. SetPort initializes I/O on first call */ setPort( TMS, 1 ); @@ -1858,7 +1866,7 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return( iErrorCode ); } U_BOOT_CMD( - cpld, 1, 1, do_cpld, - "Program onboard CPLD", - NULL - ); + cpld, 2, 1, do_cpld, + "program onboard CPLD", + "<xsvf-addr>" +); diff --git a/board/esd/common/xilinx_jtag/ports.c b/board/esd/common/xilinx_jtag/ports.c index ac0d7ac..f039d04 100644 --- a/board/esd/common/xilinx_jtag/ports.c +++ b/board/esd/common/xilinx_jtag/ports.c @@ -42,9 +42,7 @@ static int oldstate = 0; static int newstate = 0; static int readptr = 0; -extern long filesize; -extern const unsigned char fpgadata[]; - +extern const unsigned char *xsvfdata; /* if in debugging mode, then just set the variables */ void setPort(short p,short val) @@ -86,10 +84,10 @@ void pulseClock(void) void readByte(unsigned char *data) { /* pretend reading using a file */ - *data = fpgadata[readptr++]; - newstate = (100 * filepos++) / filesize; + *data = xsvfdata[readptr++]; + newstate = filepos++ >> 10; if (newstate != oldstate) { - printf("%4d\r\r\r\r", newstate); + printf("%4d kB\r\r\r\r", newstate); oldstate = newstate; } } diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index aba240f..cd57ed4 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -183,6 +183,6 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( eepwren, 2, 0, do_eep_wren, "Enable / disable / query EEPROM write access", - NULL - ); + "" +); #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index ccbe245..a677c62 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -690,8 +690,8 @@ int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( onewire, 1, 1, do_onewire, "Read 1-write ID", - NULL - ); + "" +); #define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */ #define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */ @@ -751,8 +751,8 @@ int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( getbpip, 1, 1, do_get_bpip, "Update IP-Address with Backplane IP-Address", - NULL - ); + "" +); /* * Set and print backplane ip... @@ -787,7 +787,7 @@ int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( setbpip, 2, 1, do_set_bpip, "Write Backplane IP-Address", - NULL - ); + "" +); #endif /* CONFIG_CPCI405AB */ diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c index b6b50fb..36fcf7f 100644 --- a/board/esd/cpci5200/cpci5200.c +++ b/board/esd/cpci5200/cpci5200.c @@ -295,4 +295,6 @@ int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD(writepci, 3, 1, do_writepci, "Write some data to pcibus", - "<addr> <size>\n" " - Write some data to pcibus.\n"); + "<addr> <size>\n" + "" +); diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c index 4826633..2ae4cbd 100644 --- a/board/esd/cpci750/cpci750.c +++ b/board/esd/cpci750/cpci750.c @@ -122,6 +122,9 @@ static char show_config_tab[][15] = {{"PCI0DLL_2 "}, /* 31 */ extern flash_info_t flash_info[]; +extern int do_bootm (cmd_tbl_t *, int, int, char *[]); +extern int do_bootvx (cmd_tbl_t *, int, int, char *[]); + /* ------------------------------------------------------------------------- */ /* this is the current GT register space location */ @@ -137,6 +140,15 @@ void board_prebootm_init (void); unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS; int display_mem_map (void); +/* + * Skip video initialization on slave variant. + * This function will overwrite the weak default in cfb_console.c + */ +int board_video_skip(void) +{ + return CPCI750_SLAVE_TEST; +} + /* ------------------------------------------------------------------------- */ /* @@ -184,6 +196,7 @@ original ppcboot 1.1.6 source end */ static void gt_pci_config (void) { unsigned int stat; + unsigned int data; unsigned int val = 0x00fff864; /* DINK32: BusNum 23:16, DevNum 15:11, FuncNum 10:8, RegNum 7:2 */ /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's @@ -251,10 +264,15 @@ static void gt_pci_config (void) /*ronen update the pci internal registers base address.*/ #ifdef MAP_PCI - for (stat = 0; stat <= PCI_HOST1; stat++) + for (stat = 0; stat <= PCI_HOST1; stat++) { + data = pciReadConfigReg(stat, + PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, + SELF); + data = (data & 0x0f) | CONFIG_SYS_GT_REGS; pciWriteConfigReg (stat, PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS, - SELF, CONFIG_SYS_GT_REGS); + SELF, data); + } #endif } @@ -448,13 +466,16 @@ int misc_init_r () void after_reloc (ulong dest_addr, gd_t * gd) { + memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, + CONFIG_SYS_BOOT_SIZE); - memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE); + display_mem_map (); + GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); + GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe); - display_mem_map (); - /* now, jump to the main ppcboot board init code */ - board_init_r (gd, dest_addr); - /* NOTREACHED */ + /* now, jump to the main ppcboot board init code */ + board_init_r (gd, dest_addr); + /* NOTREACHED */ } /* ------------------------------------------------------------------------- */ @@ -538,6 +559,79 @@ int display_mem_map (void) return (0); } +/* + * Command loadpci: wait for signal from host and boot image. + */ +int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + volatile unsigned int *ptr; + int count = 0; + int count2 = 0; + int status; + char addr[16]; + char str[] = "\\|/-"; + char *local_args[2]; + + /* + * Mark sync address + */ + ptr = 0; + ptr[0] = 0xffffffff; + ptr[1] = 0xffffffff; + puts("\nWaiting for image from pci host -"); + + /* + * Wait for host to write the start address + */ + while (*ptr == 0xffffffff) { + count++; + if (!(count % 100)) { + count2++; + putc(0x08); /* backspace */ + putc(str[count2 % 4]); + } + + /* Abort if ctrl-c was pressed */ + if (ctrlc()) { + puts("\nAbort\n"); + return 0; + } + + udelay(1000); + } + + sprintf(addr, "%08x", *ptr); + printf("\nBooting Image at addr 0x%s ...\n", addr); + setenv("loadaddr", addr); + + switch (ptr[1] == 0) { + case 0: + /* + * Boot image via bootm + */ + local_args[0] = argv[0]; + local_args[1] = NULL; + status = do_bootm (cmdtp, 0, 1, local_args); + break; + case 1: + /* + * Boot image via bootvx + */ + local_args[0] = argv[0]; + local_args[1] = NULL; + status = do_bootvx (cmdtp, 0, 1, local_args); + break; + } + + return 0; +} + +U_BOOT_CMD( + loadpci, 1, 1, do_loadpci, + "loadpci - Wait for pci-image and boot it\n", + NULL + ); + /* DRAM check routines copied from gw8260 */ #if defined (CONFIG_SYS_DRAM_TEST) @@ -994,5 +1088,5 @@ int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( show_config, 1, 1, do_show_config, "Show Marvell strapping register", - "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n" - ); + "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)" +); diff --git a/board/esd/cpci750/i2c.c b/board/esd/cpci750/i2c.c index d95567f..b752903 100644 --- a/board/esd/cpci750/i2c.c +++ b/board/esd/cpci750/i2c.c @@ -27,6 +27,7 @@ #include <common.h> #include <mpc8xx.h> #include <malloc.h> +#include <i2c.h> #include "../../Marvell/include/mv_gen_reg.h" #include "../../Marvell/include/core.h" @@ -41,7 +42,7 @@ /* Assuming that there is only one master on the bus (us) */ -static void i2c_init (int speed, int slaveaddr) +void i2c_init (int speed, int slaveaddr) { unsigned int n, m, freq, margin, power; unsigned int actualN = 0, actualM = 0; @@ -375,7 +376,7 @@ i2c_set_dev_offset (uchar dev_addr, unsigned int offset, int ten_bit, return 0; /* sucessful completion */ } -uchar +int i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, int len) { @@ -384,7 +385,8 @@ i2c_read (uchar dev_addr, unsigned int offset, int alen, uchar * data, DP (puts ("i2c_read\n")); - i2c_init (i2cFreq, 0); /* set the i2c frequency */ + /* set the i2c frequency */ + i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ if (status) { @@ -423,7 +425,7 @@ void i2c_stop (void) } -uchar +int i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, int len) { @@ -432,7 +434,8 @@ i2c_write (uchar dev_addr, unsigned int offset, int alen, uchar * data, DP (puts ("i2c_write\n")); - i2c_init (i2cFreq, 0); /* set the i2c frequency */ + /* set the i2c frequency */ + i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); status = i2c_set_dev_offset (dev_addr, offset, 0, alen); /* send the slave address + offset */ if (status) { @@ -468,7 +471,8 @@ int i2c_probe (uchar chip) DP (puts ("i2c_probe\n")); - i2c_init (i2cFreq, 0); /* set the i2c frequency */ + /* set the i2c frequency */ + i2c_init (i2cFreq, CONFIG_SYS_I2C_SLAVE); status = i2c_set_dev_offset (chip, 0, 0, 0); /* send the slave address + no offset */ if (status) { diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c index 9bdc523..638219f 100644 --- a/board/esd/cpci750/ide.c +++ b/board/esd/cpci750/ide.c @@ -39,6 +39,8 @@ int ide_preinit (void) int l; status = 1; + if (CPCI750_SLAVE_TEST != 0) + return status; for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) { ide_bus_offset[l] = -ATA_STATUS; } @@ -57,7 +59,7 @@ int ide_preinit (void) ide_bus_offset[1] &= 0xfffffffe; ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE; } - return (status); + return status; } void ide_set_reset (int flag) { diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c index bfc7e55..a2c1c50 100644 --- a/board/esd/cpci750/pci.c +++ b/board/esd/cpci750/pci.c @@ -768,11 +768,12 @@ static int gt_read_config_dword (struct pci_controller *hose, int bus = PCI_BUS (dev); if ((bus == local_buses[0]) || (bus == local_buses[1])) { - *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset, + *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, + offset | (PCI_FUNC(dev) << 8), PCI_DEV (dev)); } else { - *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose-> - cfg_addr, offset, + *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->cfg_addr, + offset | (PCI_FUNC(dev) << 8), PCI_DEV (dev), bus); } @@ -785,11 +786,13 @@ static int gt_write_config_dword (struct pci_controller *hose, int bus = PCI_BUS (dev); if ((bus == local_buses[0]) || (bus == local_buses[1])) { - pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset, + pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, + offset | (PCI_FUNC(dev) << 8), PCI_DEV (dev), value); } else { pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr, - offset, PCI_DEV (dev), bus, + offset | (PCI_FUNC(dev) << 8), + PCI_DEV (dev), bus, value); } return 0; @@ -803,6 +806,9 @@ static void gt_setup_ide (struct pci_controller *hose, u32 bar_response, bar_value; int bar; + if (CPCI750_SLAVE_TEST != 0) + return; + for (bar = 0; bar < 6; bar++) { /*ronen different function for 3rd bank. */ unsigned int offset = @@ -829,6 +835,9 @@ static void gt_setup_cpcidvi (struct pci_controller *hose, { u32 bar_value, pci_response; + if (CPCI750_SLAVE_TEST != 0) + return; + pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response); pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff); pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response); @@ -907,6 +916,7 @@ struct pci_controller pci1_hose = { void pci_init_board (void) { unsigned int command; + unsigned int slave; #ifdef CONFIG_PCI_PNP unsigned int bar; #endif @@ -918,6 +928,8 @@ void pci_init_board (void) gt_cpcidvi_rom.base = 0; #endif + slave = CPCI750_SLAVE_TEST; + pci0_hose.config_table = gt_config_table; pci1_hose.config_table = gt_config_table; @@ -953,27 +965,40 @@ void pci_init_board (void) pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0; pci_register_hose (&pci0_hose); - pciArbiterEnable (PCI_HOST0); - pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MASTER; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); - command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); - command |= PCI_COMMAND_MEMORY; - pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); + if (slave == 0) { + pciArbiterEnable (PCI_HOST0); + pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); + command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MASTER; + pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); + command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MEMORY; + pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); #ifdef CONFIG_PCI_PNP - pciauto_config_init(&pci0_hose); - pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar); + pciauto_config_init(&pci0_hose); + pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar); #endif #ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); + printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif - pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno); + pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, + pci0_hose.first_busno); #ifdef DEBUG - gt_pci_bus_mode_display (PCI_HOST1); + gt_pci_bus_mode_display (PCI_HOST1); #endif + } else { + pciArbiterDisable (PCI_HOST0); + pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1); + command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MASTER; + pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); + command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF); + command |= PCI_COMMAND_MEMORY; + pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command); + pci0_hose.last_busno = pci0_hose.first_busno; + } pci1_hose.first_busno = pci0_hose.last_busno + 1; pci1_hose.last_busno = 0xff; pci1_hose.current_busno = pci1_hose.first_busno; diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c index 0310c47..675e507 100644 --- a/board/esd/dasa_sim/cmd_dasa_sim.c +++ b/board/esd/dasa_sim/cmd_dasa_sim.c @@ -230,7 +230,7 @@ U_BOOT_CMD( pci9054, 3, 1, do_pci9054, "PLX PCI9054 EEPROM access", "pci9054 info - print EEPROM values\n" - "pci9054 update - updates EEPROM with default values\n" + "pci9054 update - updates EEPROM with default values" ); /* ------------------------------------------------------------------------- */ diff --git a/board/esd/dp405/config.mk b/board/esd/dp405/config.mk index 3041b77..9b1a8be 100644 --- a/board/esd/dp405/config.mk +++ b/board/esd/dp405/config.mk @@ -21,9 +21,4 @@ # MA 02111-1307 USA # -# -# esd VOH405 boards -# - -TEXT_BASE = 0xFFFC0000 -#TEXT_BASE = 0x00FC0000 +TEXT_BASE = 0xFFFD0000 diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c index c32c7c7..8f4b78d 100644 --- a/board/esd/dp405/dp405.c +++ b/board/esd/dp405/dp405.c @@ -29,14 +29,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* fpga configuration data - not compressed, generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; -int filesize = sizeof(fpgadata); - - int board_early_init_f (void) { /* @@ -97,20 +89,40 @@ int checkboard (void) int i = getenv_r ("serial#", str, sizeof(str)); unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe, 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf}; - unsigned char id1, id2; + unsigned char id1, id2, rev; puts ("Board: "); - if (i == -1) { + if (i == -1) puts ("### No HW ID - assuming DP405"); - } else { + else puts(str); - } id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f]; id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f]; - printf(" (ID=0x%1X%1X, PLD=0x%02X)\n", - id2, id1, in_8((void *)0xf0001000)); + + rev = in_8((void *)0xf0001000); + if (rev & 0x10) /* old DP405 compatibility */ + rev = in_8((void *)0xf0000800); + + switch (rev & 0xc0) { + case 0x00: + puts(" (HW=DP405"); + break; + case 0x80: + puts(" (HW=DP405/CO"); + break; + case 0xc0: + puts(" (HW=DN405"); + break; + } + printf(", ID=0x%1X%1X, PLD=0x%02X", id2, id1, rev & 0x0f); + + if ((rev & 0xc0) == 0xc0) { + printf(", C5V=%s", + in_be32((void *)GPIO0_IR) & 0x40000000 ? "off" : "on"); + } + puts(")\n"); return 0; } diff --git a/board/esd/dp405/fpgadata.c b/board/esd/dp405/fpgadata.c deleted file mode 100644 index eae8457..0000000 --- a/board/esd/dp405/fpgadata.c +++ /dev/null @@ -1,1812 +0,0 @@ - 0x07,0x20,0x12,0x00,0x12,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08, - 0xfe,0x08,0x00,0x00,0x00,0x20,0x01,0x0f,0xff,0xff,0xff,0x09,0x00,0x00,0x00,0x00, - 0xf9,0x60,0x40,0x93,0x02,0x08,0xff,0x02,0x08,0xff,0x02,0x08,0xe8,0x08,0x00,0x00, - 0x00,0x06,0x01,0x00,0x09,0x05,0x00,0x02,0x08,0xed,0x04,0x00,0x03,0x0d,0x40,0x08, - 0x00,0x00,0x00,0x12,0x01,0x00,0x00,0x00,0x09,0x03,0xff,0xff,0x00,0x00,0x00,0x01, - 0x00,0x00,0x03,0x09,0x03,0xff,0xfd,0x03,0xff,0xfd,0x04,0x00,0x00,0x00,0x00,0x02, - 0x08,0xea,0x08,0x00,0x00,0x00,0x32,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09, - 0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x04,0x00,0x00,0x00,0x01,0x00,0x00, - 0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00, - 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0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc8,0x08,0x00,0x00,0x01,0x00,0x00,0x00,0x00, - 0x00,0x00,0x01,0x09,0x00,0x35,0xcc,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00, - 0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09, - 0x00,0x35,0xd0,0x00,0x00,0x80,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00, - 0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0xd0,0x00,0x00,0x80,0x01,0x00,0x00, - 0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x04,0x00,0x00, - 0x00,0x64,0x02,0x08,0xf0,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,0xff, - 0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00,0x00,0x00, diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 45dfa6f..0ec519b 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -607,8 +607,8 @@ int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( dcf77, 1, 1, do_dcf77, "Check DCF77 receiver", - NULL - ); + "" +); /* * initialize USB hub via I2C1 @@ -657,8 +657,8 @@ int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( hubinit, 1, 1, do_hubinit, "Initialize USB hub", - NULL - ); + "" +); #endif /* CONFIG_I2C_MULTI_BUS */ #define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3 @@ -790,8 +790,8 @@ int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( sbe, 2, 0, do_setup_boot_eeprom, "setup boot eeprom", - NULL - ); + "" +); #if defined(CONFIG_SYS_EEPROM_WREN) /* @@ -863,8 +863,9 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - NULL); + "Enable / disable / query EEPROM write access", + "" +); #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ static int got_pldirq; @@ -916,8 +917,8 @@ int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( wpi, 1, 1, do_waitpwrirq, "Wait for power change interrupt", - NULL - ); + "" +); /* * initialize DVI panellink transmitter @@ -961,8 +962,8 @@ int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( dviinit, 1, 1, do_dviinit, "Initialize DVI Panellink transmitter", - NULL - ); + "" +); /* * TODO: 'time' command might be useful for others as well. @@ -1001,8 +1002,8 @@ int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( time, CONFIG_SYS_MAXARGS, 1, do_time, "run command and output execution time", - NULL - ); + "" +); extern void video_hw_rectfill ( unsigned int bpp, /* bytes per pixel */ @@ -1051,5 +1052,5 @@ int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo, "demo", - NULL - ); + "" +); diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index eab952c..5ae4c75 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -769,8 +769,9 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - NULL); + "Enable / disable / query EEPROM write access", + "" +); #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/mecp5123/Makefile b/board/esd/mecp5123/Makefile new file mode 100644 index 0000000..2e3d73a --- /dev/null +++ b/board/esd/mecp5123/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2009 Wolfgang Denk <wd@denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/esd/mecp5123/config.mk b/board/esd/mecp5123/config.mk new file mode 100644 index 0000000..838a018 --- /dev/null +++ b/board/esd/mecp5123/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2009 Wolfgang Denk <wd@denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFF00000 diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c new file mode 100644 index 0000000..909b458 --- /dev/null +++ b/board/esd/mecp5123/mecp5123.c @@ -0,0 +1,381 @@ +/* + * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> + * (C) Copyright 2009 Dave Srl www.dave.eu + * (C) Copyright 2009 Stefan Roese <sr@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/bitops.h> +#include <command.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <fdt_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Clocks in use */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_NFC_EN | \ + CLOCK_SCCR1_PCI_EN | \ + CLOCK_SCCR1_TPR_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_I2C_EN) + +#define CSAW_START(start) ((start) & 0xFFFF0000) +#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) + +int eeprom_write_enable(unsigned dev_addr, int state) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + + if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR) + return -1; + + if (state == 0) + setbits_be32(&im->gpio.gpdat, 0x00100000); + else + clrbits_be32(&im->gpio.gpdat, 0x00100000); + +return 0; +} + +/* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync. + */ +static inline void sync_law(volatile void *addr) +{ + in_be32(addr); + __asm__ __volatile__ ("isync"); +} + +int board_early_init_f(void) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 spridr; + + /* + * Initialize Local Window for NOR FLASH access + */ + out_be32(&im->sysconf.lpcs0aw, + CSAW_START(CONFIG_SYS_FLASH_BASE) | + CSAW_STOP(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)); + sync_law(&im->sysconf.lpcs0aw); + + /* + * Initialize Local Window for boot access + */ + out_be32(&im->sysconf.lpbaw, + CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000)); + sync_law(&im->sysconf.lpbaw); + + /* + * Initialize Local Window for VPC3 access + */ + out_be32(&im->sysconf.lpcs1aw, + CSAW_START(CONFIG_SYS_VPC3_BASE) | + CSAW_STOP(CONFIG_SYS_VPC3_BASE, CONFIG_SYS_VPC3_SIZE)); + sync_law(&im->sysconf.lpcs1aw); + + /* + * Configure Flash Speed + */ + out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); + + /* + * Configure VPC3 Speed + */ + out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG); + + spridr = in_be32(&im->sysconf.spridr); + if (SVR_MJREV(spridr) >= 2) + out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); + + /* + * Enable clocks + */ + out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); + out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN); +#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) + setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); +#endif + + /* + * Configure MSCAN clocks + */ + out_be32(&im->clk.m1ccr, 0x00300000); + out_be32(&im->clk.m2ccr, 0x00300000); + out_be32(&im->clk.m3ccr, 0x00300000); + out_be32(&im->clk.m4ccr, 0x00300000); + out_be32(&im->clk.m1ccr, 0x00310000); + out_be32(&im->clk.m2ccr, 0x00310000); + out_be32(&im->clk.m3ccr, 0x00310000); + out_be32(&im->clk.m4ccr, 0x00310000); + + /* + * Configure GPIO's + */ + clrbits_be32(&im->gpio.gpodr, 0x000000e0); + clrbits_be32(&im->gpio.gpdir, 0x00ef0000); + setbits_be32(&im->gpio.gpdir, 0x001000e0); + setbits_be32(&im->gpio.gpdat, 0x00100000); + + return 0; +} + +/* + * fixed sdram init: + * The board doesn't use memory modules that have serial presence + * detect or similar mechanism for discovery of the DRAM settings + */ +long int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + u32 i; + + /* Initialize IO Control */ + out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR); + + /* Initialize DDR Local Window */ + out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000); + out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1); + sync_law(&im->sysconf.ddrlaw.ar); + + /* Enable DDR */ + out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN); + + /* Initialize DDR Priority Manager */ + out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1); + out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2); + out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG); + out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU); + out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML); + out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU); + out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML); + out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU); + out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML); + out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU); + out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML); + out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU); + out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML); + out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU); + out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL); + out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU); + out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL); + out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU); + out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL); + out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU); + out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL); + out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU); + out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL); + + /* Initialize MDDRC */ + out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG); + out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0); + out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1); + out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2); + + /* Initialize DDR */ + for (i = 0; i < 10; i++) + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + + /* Start MDDRC */ + out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN); + out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN); + + return msize; +} + +phys_size_t initdram(int board_type) +{ + return get_ram_size(0, fixed_sdram()); +} + +int misc_init_r(void) +{ + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + u32 val; + + /* + * Optimize access to profibus chip (VPC3) on the local bus + */ + + /* + * Select 1:1 for LPC_DIV + */ + val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK; + out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT)); + + /* + * Configure LPC Chips Select Deadcycle Control Register + * CS0 - device can drive data 2 clock cycle(s) after CS deassertion + * CS1 - device can drive data 1 clock cycle(s) after CS deassertion + */ + clrbits_be32(&im->lpc.cs_dccr, 0x000000ff); + setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0)); + + /* + * Configure LPC Chips Select Holdcycle Control Register + * CS0 - data is valid 2 clock cycle(s) after CS deassertion + * CS1 - data is valid 1 clock cycle(s) after CS deassertion + */ + clrbits_be32(&im->lpc.cs_hccr, 0x000000ff); + setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0)); + + return 0; +} + +static iopin_t ioregs_init[] = { + /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */ + { + offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0, + IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC1=FEC_COL Sets Next 15 to FEC pads */ + { + offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0, + IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC1=SELECT LPC_CS1 */ + { + offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0, + IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=SELECT PSC5_2 */ + { + offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0, + IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=SELECT PSC5_3 */ + { + offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0, + IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=SELECT PSC7_3 */ + { + offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0, + IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=SELECT PSC9_0 */ + { + offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0, + IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=SELECT PSC10_0 */ + { + offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0, + IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=SELECT PSC10_3 */ + { + offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0, + IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC3=SELECT PSC11_0 */ + { + offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0, + IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC0=SELECT IRQ0 */ + { + offsetof(struct ioctrl512x, io_control_irq0), 4, 0, + IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } +}; + +static iopin_t rev2_silicon_pci_ioregs_init[] = { + /* FUNC0=PCI Sets next 54 to PCI pads */ + { + offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0, + IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0) + } +}; + +int checkboard(void) +{ + volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 spridr; + + puts("Board: MECP_5123\n"); + + /* + * Initialize function mux & slew rate IO inter alia on IO + * Pins + */ + iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init)); + + spridr = in_be32(&im->sysconf.spridr); + if (SVR_MJREV(spridr) >= 2) + iopin_initialize(rev2_silicon_pci_ioregs_init, 1); + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c index db2c548..5f3254d 100644 --- a/board/esd/ocrtc/cmd_ocrtc.c +++ b/board/esd/ocrtc/cmd_ocrtc.c @@ -55,7 +55,7 @@ int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( setdevice, 1, 1, do_setdevice, "Set device number on pci adapter boards", - NULL + "" ); @@ -78,7 +78,7 @@ int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( getdevice, 1, 1, do_getdevice, "Get device number and set slot env variable", - NULL + "" ); #endif diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c index a0d1f3f..1d14611 100644 --- a/board/esd/pci405/cmd_pci405.c +++ b/board/esd/pci405/cmd_pci405.c @@ -109,6 +109,6 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( loadpci, 1, 1, do_loadpci, "Wait for pci-image and boot it", - NULL + "" ); #endif diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index 8973f97..56184ca 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -381,5 +381,5 @@ U_BOOT_CMD( "wpeeprom 1\n" " - enable I2C EEPROM write protection\n" "wpeeprom 0\n" - " - disable I2C EEPROM write protection\n" - ); + " - disable I2C EEPROM write protection" +); diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c index f225f0e..4e64e83 100644 --- a/board/esd/pf5200/pf5200.c +++ b/board/esd/pf5200/pf5200.c @@ -294,7 +294,7 @@ int do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return (0); } -U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "Switch off power", NULL); +U_BOOT_CMD(poweroff, 1, 1, do_poweroff, "Switch off power", ""); int phypower(int flag) { @@ -338,7 +338,7 @@ int do_phypower(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(phypower, 2, 2, do_phypower, - "Switch power of ethernet phy", NULL); + "Switch power of ethernet phy", ""); int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { @@ -369,5 +369,7 @@ int do_writepci(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(writepci, 3, 1, do_writepci, - "Write some data to pcibus", - "<addr> <size>\n" " - Write some data to pcibus.\n"); + "Write some data to pcibus", + "<addr> <size>\n" + "" +); diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index a94604a..fdacbf6 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -333,6 +333,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - NULL); + "Enable / disable / query EEPROM write access", + "" +); #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/pmc405/fpgadata.c b/board/esd/pmc405/fpgadata.c deleted file mode 100644 index ebdf71d..0000000 --- a/board/esd/pmc405/fpgadata.c +++ /dev/null @@ -1,2472 +0,0 @@ - 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0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00, - 0x00,0x00, diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 94caa6c..192a642 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -34,13 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; extern void lxt971_no_sleep(void); -/* fpga configuration data - not compressed, generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; -int filesize = sizeof(fpgadata); - int board_early_init_f (void) { /* diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index 0fbc3dc..1af431b 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -99,8 +99,8 @@ int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( waithci, 1, 1, do_waithci, "Wait for host control interrupt", - NULL - ); + "" +); void dump_fifo(pmc440_fpga_t *fpga, int f, int *n) { @@ -266,8 +266,8 @@ U_BOOT_CMD( " - with 'wait' argument: interrupt driven read from all fifos\n" " - with 'read' argument: read current contents from all fifos\n" " - with 'write' argument: write 'data' 'cnt' times to " - "'fifo' or 'address'\n" - ); + "'fifo' or 'address'" +); int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -338,7 +338,7 @@ U_BOOT_CMD( sbe, 4, 0, do_setup_bootstrap_eeprom, "setup bootstrap eeprom", "<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]" - ); +); #if defined(CONFIG_PRAM) #include <environment.h> @@ -400,8 +400,8 @@ int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( painit, 1, 1, do_painit, "prepare PciAccess system", - NULL - ); + "" +); #endif /* CONFIG_PRAM */ int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -412,8 +412,8 @@ int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( selfreset, 1, 1, do_selfreset, "assert self-reset# signal", - NULL - ); + "" +); int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -449,8 +449,8 @@ int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( resetout, 2, 1, do_resetout, "assert PMC-RESETOUT# signal", - NULL - ); + "" +); int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -481,8 +481,8 @@ int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( inta, 2, 1, do_inta, "Assert/Deassert or query INTA# state in non-monarch mode", - NULL - ); + "" +); /* test-only */ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -514,8 +514,8 @@ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( pmm, 2, 1, do_pmm, "Setup pmm[1] registers", - "<pciaddr> (pciaddr will be aligned to 256MB)\n" - ); + "<pciaddr> (pciaddr will be aligned to 256MB)" +); #if defined(CONFIG_SYS_EEPROM_WREN) int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) @@ -549,8 +549,9 @@ int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return state; } U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - NULL); + "Enable / disable / query EEPROM write access", + "" +); #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ #endif /* CONFIG_CMD_BSP */ diff --git a/board/esd/tasreg/tasreg.c b/board/esd/tasreg/tasreg.c index 760c71d..1844442 100644 --- a/board/esd/tasreg/tasreg.c +++ b/board/esd/tasreg/tasreg.c @@ -231,7 +231,7 @@ int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr = simple_strtol (argv[1], NULL, 16); - printf("iprobe looping on addr 0x%lx (cntrl-c aborts)...\n", addr); + printf("i2c probe looping on addr 0x%lx (cntrl-c aborts)...\n", addr); for (;;) { i2c_probe(addr); @@ -249,9 +249,9 @@ int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD( iploop, 2, 1, do_iploop, - "iprobe loop <addr>", - NULL - ); + "i2c probe loop <addr>", + "" +); /* */ @@ -303,8 +303,8 @@ int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( codec, 1, 1, do_codec, "Enable codec", - NULL - ); + "" +); /* */ @@ -336,8 +336,8 @@ int do_saa(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( saa, 5, 1, do_saa, "Write to SAA1064 <addr> <instr> <cntrl> <data>", - NULL - ); + "" +); /* */ @@ -375,8 +375,8 @@ int do_iwrite(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( iwrite, 6, 1, do_iwrite, "Write n bytes to I2C-device", - "addr cnt data0 ... datan\n" - ); + "addr cnt data0 ... datan" +); /* */ @@ -407,8 +407,8 @@ int do_iread(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( iread, 3, 1, do_iread, "Read from I2C <addr> <cnt>", - NULL - ); + "" +); /* */ @@ -445,6 +445,6 @@ int do_ireadl(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( ireadl, 2, 1, do_ireadl, "Read-loop from I2C <addr>", - NULL - ); + "" +); #endif diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 96a04b3..9127550 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -392,6 +392,7 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } U_BOOT_CMD(eepwren, 2, 0, do_eep_wren, - "Enable / disable / query EEPROM write access", - NULL); + "Enable / disable / query EEPROM write access", + "" +); #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */ diff --git a/board/esd/vom405/config.mk b/board/esd/vom405/config.mk index 3041b77..8e48bcd 100644 --- a/board/esd/vom405/config.mk +++ b/board/esd/vom405/config.mk @@ -20,10 +20,4 @@ # Foundation, Inc., 59 Temple Place, Suite 330, Boston, # MA 02111-1307 USA # - -# -# esd VOH405 boards -# - -TEXT_BASE = 0xFFFC0000 -#TEXT_BASE = 0x00FC0000 +TEXT_BASE = 0xFFFC8000 diff --git a/board/esd/vom405/fpgadata.c b/board/esd/vom405/fpgadata.c deleted file mode 100644 index 1c3a963..0000000 --- a/board/esd/vom405/fpgadata.c +++ /dev/null @@ -1,1812 +0,0 @@ - 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0x00,0x35,0xd0,0x88,0x00,0x04,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00, - 0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0xd0,0x88,0x00,0x04,0x01,0x00,0x00, - 0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x04,0x00,0x00, - 0x00,0x64,0x02,0x08,0xf0,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,0xff, - 0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00,0x00,0x00, diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c index d67b23e..a481aca 100644 --- a/board/esd/vom405/vom405.c +++ b/board/esd/vom405/vom405.c @@ -31,13 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; extern void lxt971_no_sleep(void); -/* fpga configuration data - not compressed, generated by bin2c */ -const unsigned char fpgadata[] = -{ -#include "fpgadata.c" -}; -int filesize = sizeof(fpgadata); - int board_early_init_f (void) { /* |