diff options
| author | Matthias Fuchs <matthias.fuchs@esd-electronics.com> | 2008-03-30 18:01:15 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-03-31 11:47:09 +0200 |
| commit | 7c91f51a2fe296909147f1646a1412729dd10b1d (patch) | |
| tree | abb90b794d51c16ddc1c52cae2e55c5c1e21a2e3 /board/esd | |
| parent | cc8e839abc80887ae832767b5930d40edd6d7eb7 (diff) | |
| download | u-boot-imx-7c91f51a2fe296909147f1646a1412729dd10b1d.zip u-boot-imx-7c91f51a2fe296909147f1646a1412729dd10b1d.tar.gz u-boot-imx-7c91f51a2fe296909147f1646a1412729dd10b1d.tar.bz2 | |
ppc4xx: Minor updates for DU440 boards
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Diffstat (limited to 'board/esd')
| -rw-r--r-- | board/esd/du440/du440.c | 5 | ||||
| -rw-r--r-- | board/esd/du440/du440.h | 1 |
2 files changed, 4 insertions, 2 deletions
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index ceb128c..3dbb2e1 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -67,12 +67,12 @@ int board_early_init_f(void) out_be32((void*)GPIO1_OR, 0x00000000); out_be32((void*)GPIO1_TCR, 0xc2000000 | CFG_GPIO1_IORSTN | + CFG_GPIO1_IORST2N | CFG_GPIO1_LEDUSR1 | CFG_GPIO1_LEDUSR2 | CFG_GPIO1_LEDPOST | CFG_GPIO1_LEDDU); out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU); - out_be32((void*)GPIO1_OSRL, 0x5c280000); out_be32((void*)GPIO1_OSRH, 0x00000000); out_be32((void*)GPIO1_TSRL, 0x0c000000); @@ -243,7 +243,8 @@ int misc_init_r(void) * release IO-RST# * We have to wait at least 560ms until we may call usbhub_init */ - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_IORSTN); + out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | + CFG_GPIO1_IORSTN | CFG_GPIO1_IORST2N); /* * flash USR1/2 LEDs (600ms) diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h index 5c362e4..83fdac7 100644 --- a/board/esd/du440/du440.h +++ b/board/esd/du440/du440.h @@ -24,6 +24,7 @@ #define CFG_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */ #define CFG_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */ +#define CFG_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */ #define CFG_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */ #define CFG_GPIO1_HWVER_SHIFT 4 |