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| author | Stefan Roese <sr@denx.de> | 2008-08-13 06:47:12 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-08-13 06:47:12 +0200 |
| commit | 5a7ddf4e1fb9347f783eb1473c30187d7a22bd81 (patch) | |
| tree | 5e30fc06d7bbd5b382b1a7b89f57cd81a5246f32 /board/esd | |
| parent | 9939ffd5fbf1f5aff4d8172531d4fc33797c62c8 (diff) | |
| parent | 8641ff266ae6638da201747c239fd39ba34c4958 (diff) | |
| download | u-boot-imx-5a7ddf4e1fb9347f783eb1473c30187d7a22bd81.zip u-boot-imx-5a7ddf4e1fb9347f783eb1473c30187d7a22bd81.tar.gz u-boot-imx-5a7ddf4e1fb9347f783eb1473c30187d7a22bd81.tar.bz2 | |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'board/esd')
| -rw-r--r-- | board/esd/common/esd405ep_nand.c | 42 |
1 files changed, 20 insertions, 22 deletions
diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c index 7bf6847..40d1efb 100644 --- a/board/esd/common/esd405ep_nand.c +++ b/board/esd/common/esd405ep_nand.c @@ -30,28 +30,26 @@ /* * hardware specific access to control-lines */ -static void esd405ep_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd) +static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - switch(cmd) { - case NAND_CTL_SETCLE: - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE); - break; - case NAND_CTL_CLRCLE: - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE); - break; - case NAND_CTL_SETALE: - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE); - break; - case NAND_CTL_CLRALE: - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE); - break; - case NAND_CTL_SETNCE: - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE); - break; - case NAND_CTL_CLRNCE: - out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); - break; + struct nand_chip *this = mtd->priv; + if (ctrl & NAND_CTRL_CHANGE) { + if ( ctrl & NAND_CLE ) + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE); + else + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE); + if ( ctrl & NAND_ALE ) + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE); + else + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE); + if ( ctrl & NAND_NCE ) + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE); + else + out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE); } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); } @@ -77,9 +75,9 @@ int board_nand_init(struct nand_chip *nand) /* * Initialize nand_chip structure */ - nand->hwcontrol = esd405ep_nand_hwcontrol; + nand->cmd_ctrl = esd405ep_nand_hwcontrol; nand->dev_ready = esd405ep_nand_device_ready; - nand->eccmode = NAND_ECC_SOFT; + nand->ecc.mode = NAND_ECC_SOFT; nand->chip_delay = NAND_BIG_DELAY_US; nand->options = NAND_SAMSUNG_LP_OPTIONS; return 0; |