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authorJon Loeliger <jdl@freescale.com>2008-01-03 09:46:55 -0600
committerJon Loeliger <jdl@freescale.com>2008-01-03 09:46:55 -0600
commit2c3536425d987bf079258973e2acebaaef3e16b6 (patch)
tree659d06dd33eca4888e1f6d01d046507b76dc2d27 /board/esd/voh405/voh405.c
parentf743931f9b4d4e15c9bdfe726bef033ea1f1402c (diff)
parentce37422d0002e10490e268392e0c4e3028e52cec (diff)
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Merge commit 'wd/master'
Diffstat (limited to 'board/esd/voh405/voh405.c')
-rw-r--r--board/esd/voh405/voh405.c135
1 files changed, 116 insertions, 19 deletions
diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c
index 2857a0be..87a5849 100644
--- a/board/esd/voh405/voh405.c
+++ b/board/esd/voh405/voh405.c
@@ -22,6 +22,7 @@
*/
#include <common.h>
+#include <asm/io.h>
#include <asm/processor.h>
#include <command.h>
#include <malloc.h>
@@ -112,11 +113,11 @@ int misc_init_f (void)
int misc_init_r (void)
{
- volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
- volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
- volatile unsigned short *lcd_contrast =
+ unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
+ unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
+ unsigned short *lcd_contrast =
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
- volatile unsigned short *lcd_backlight =
+ unsigned short *lcd_backlight =
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
unsigned char *dst;
ulong len = sizeof(fpgadata);
@@ -180,25 +181,37 @@ int misc_init_r (void)
/*
* Reset FPGA via FPGA_INIT pin
*/
- out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT); /* reset low */
udelay(1000); /* wait 1ms */
- out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT); /* reset high */
udelay(1000); /* wait 1ms */
/*
* Reset external DUARTs
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
udelay(10); /* wait 10us */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
udelay(1000); /* wait 1ms */
/*
+ * Set NAND-FLASH GPIO signals to default
+ */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
+
+ /*
+ * Setup EEPROM write protection
+ */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
+
+ /*
* Enable interrupts in exar duart mcr[3]
*/
- *duart0_mcr = 0x08;
- *duart1_mcr = 0x08;
+ out_8(duart0_mcr, 0x08);
+ out_8(duart1_mcr, 0x08);
/*
* Init lcd interface and display logo
@@ -240,17 +253,23 @@ int misc_init_r (void)
/*
* Set invert bit in small lcd controller
*/
- *(unsigned char *)(CFG_LCD_SMALL_REG + 2) |= 0x01;
+ out_8((unsigned char *)(CFG_LCD_SMALL_REG + 2),
+ in_8((unsigned char *)(CFG_LCD_SMALL_REG + 2)) | 0x01);
/*
* Set default contrast voltage on epson vga controller
*/
- *lcd_contrast = 0x4646;
+ out_be16(lcd_contrast, 0x4646);
/*
* Enable backlight
*/
- *lcd_backlight = 0xffff;
+ out_be16(lcd_backlight, 0xffff);
+
+ /*
+ * Enable external I2C bus
+ */
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_IIC_ON);
return (0);
}
@@ -281,11 +300,6 @@ int checkboard (void)
putc ('\n');
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-
return 0;
}
@@ -334,3 +348,86 @@ void ide_set_reset(int on)
}
}
#endif /* CONFIG_IDE_RESET */
+
+#if defined(CONFIG_RESET_PHY_R)
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
+#endif
+
+#if defined(CFG_EEPROM_WREN)
+/* Input: <dev_addr> I2C address of EEPROM device to enable.
+ * <state> -1: deliver current state
+ * 0: disable write
+ * 1: enable write
+ * Returns: -1: wrong device address
+ * 0: dis-/en- able done
+ * 0/1: current state if <state> was -1.
+ */
+int eeprom_write_enable (unsigned dev_addr, int state)
+{
+ if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+ return -1;
+ } else {
+ switch (state) {
+ case 1:
+ /* Enable write access, clear bit GPIO0. */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
+ state = 0;
+ break;
+ case 0:
+ /* Disable write access, set bit GPIO0. */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+ state = 0;
+ break;
+ default:
+ /* Read current status back. */
+ state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
+ break;
+ }
+ }
+ return state;
+}
+
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int query = argc == 1;
+ int state = 0;
+
+ if (query) {
+ /* Query write access state. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+ if (state < 0) {
+ puts ("Query of write access state failed.\n");
+ } else {
+ printf ("Write access for device 0x%0x is %sabled.\n",
+ CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+ state = 0;
+ }
+ } else {
+ if ('0' == argv[1][0]) {
+ /* Disable write access. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+ } else {
+ /* Enable write access. */
+ state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+ }
+ if (state < 0) {
+ puts ("Setup of write access state failed.\n");
+ }
+ }
+
+ return state;
+}
+
+U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
+ "eepwren - Enable / disable / query EEPROM write access\n",
+ NULL);
+#endif /* #if defined(CFG_EEPROM_WREN) */