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authorMatthias Fuchs <matthias.fuchs@esd-electronics.com>2009-02-20 10:19:19 +0100
committerWolfgang Denk <wd@denx.de>2009-03-20 22:39:14 +0100
commitbb57ad4be76d0e2e7f9ec56678235cc9872ff40f (patch)
treed02d3c5da773f66005bd4c2151e40529d06d4c4a /board/esd/tasreg/tasreg.c
parent049216f045fd8e0f45bcef121c2bb1c7d3de6988 (diff)
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ppc4xx: Use correct io accessors for esd 405/440 boards
This patch replaces in/out8/16/32 macros by in/out_8/_be16/_be32 macros. Also volatile pointer references are replaced by the new accessors. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/esd/tasreg/tasreg.c')
-rw-r--r--board/esd/tasreg/tasreg.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/board/esd/tasreg/tasreg.c b/board/esd/tasreg/tasreg.c
index 80ff237..760c71d 100644
--- a/board/esd/tasreg/tasreg.c
+++ b/board/esd/tasreg/tasreg.c
@@ -25,6 +25,7 @@
#include <command.h>
#include <malloc.h>
#include <asm/m5249.h>
+#include <asm/io.h>
/* Prototypes */
@@ -118,7 +119,7 @@ phys_size_t initdram (int board_type) {
/** Precharge sequence **/
mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
- *((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
+ out_be32((void *)0, junk); /* write to a memory location to init. precharge */
udelay(0x10); /* Allow several Precharge cycles */
/** Refresh Sequence **/
@@ -127,7 +128,7 @@ phys_size_t initdram (int board_type) {
/** Mode Register initialization **/
mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
- *((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
+ out_be32((void *)0x800, junk); /* Access RAM to initialize the mode register */
return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
};
@@ -258,7 +259,7 @@ int do_codec(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
uchar buf[8];
- *(volatile ushort *)0xe0000000 = 0x4000;
+ out_be16((void *)0xe0000000, 0x4000);
udelay(5000); /* wait for 5ms */