diff options
author | Stefan Roese <sr@denx.de> | 2009-09-09 16:25:29 +0200 |
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committer | Stefan Roese <sr@denx.de> | 2009-09-11 10:35:58 +0200 |
commit | d1c3b27525b664e8c4db6bb173eed51bfc8220de (patch) | |
tree | c00f3d0bcfbd5fcc1954cc9cefdbc4c9c41f41ea /board/esd/ocrtc | |
parent | e7963772eb78a6aa1fa65063d64eab3a8626daac (diff) | |
download | u-boot-imx-d1c3b27525b664e8c4db6bb173eed51bfc8220de.zip u-boot-imx-d1c3b27525b664e8c4db6bb173eed51bfc8220de.tar.gz u-boot-imx-d1c3b27525b664e8c4db6bb173eed51bfc8220de.tar.bz2 |
ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/esd/ocrtc')
-rw-r--r-- | board/esd/ocrtc/flash.c | 20 | ||||
-rw-r--r-- | board/esd/ocrtc/ocrtc.c | 2 |
2 files changed, 11 insertions, 11 deletions
diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c index e763a89..eda7c57 100644 --- a/board/esd/ocrtc/flash.c +++ b/board/esd/ocrtc/flash.c @@ -68,9 +68,9 @@ unsigned long flash_init (void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); + mtdcr (EBC0_CFGADDR, PB0CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; switch (size_b1) { case 1 << 20: @@ -90,14 +90,14 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); + mtdcr (EBC0_CFGADDR, PB1CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; switch (size_b1) { case 1 << 20: @@ -117,8 +117,8 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c index 35bfa95..709bcdd 100644 --- a/board/esd/ocrtc/ocrtc.c +++ b/board/esd/ocrtc/ocrtc.c @@ -57,7 +57,7 @@ int board_early_init_f (void) * EBC Configuration Register: clear EBTC -> high-Z ebc signals between * transfers, set device-paced timeout to 256 cycles */ - mtebc (epcr, 0x20400000); + mtebc (EBC0_CFG, 0x20400000); return 0; } |