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| author | roy zang <tie-fei.zang@freescale.com> | 2007-02-12 11:24:27 +0800 |
|---|---|---|
| committer | Zang Tiefei <roy@bus.ap.freescale.net> | 2007-02-12 11:24:27 +0800 |
| commit | 30bddf2c46ab2e824f217a38db033118ac4622af (patch) | |
| tree | 2969155507e6902a7dddebad6c7c9ba259e816be /board/esd/mecp5200/mt46v16m16-75.h | |
| parent | c1c52e38d35ff01f08b55377126c979a08fbdb1d (diff) | |
| parent | b0b1a920aebead0d44146e73676ae9d80fffc8e2 (diff) | |
| download | u-boot-imx-30bddf2c46ab2e824f217a38db033118ac4622af.zip u-boot-imx-30bddf2c46ab2e824f217a38db033118ac4622af.tar.gz u-boot-imx-30bddf2c46ab2e824f217a38db033118ac4622af.tar.bz2 | |
Merge branch 'master' into hpc2
Diffstat (limited to 'board/esd/mecp5200/mt46v16m16-75.h')
| -rw-r--r-- | board/esd/mecp5200/mt46v16m16-75.h | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/board/esd/mecp5200/mt46v16m16-75.h b/board/esd/mecp5200/mt46v16m16-75.h new file mode 100644 index 0000000..22d0a55 --- /dev/null +++ b/board/esd/mecp5200/mt46v16m16-75.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_DDR 1 /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x705f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif |