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| author | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
|---|---|---|
| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
| commit | cb5473205206c7f14cbb1e747f28ec75b48826e2 (patch) | |
| tree | 8f4808d60917100b18a10b05230f7638a0a9bbcc /board/esd/mecp5200/mecp5200.c | |
| parent | baf449fc5ff96f071bb0e3789fd3265f6d4fd9a0 (diff) | |
| parent | 92c78a3bbcb2ce508b4bf1c4a1e0940406a024bb (diff) | |
| download | u-boot-imx-cb5473205206c7f14cbb1e747f28ec75b48826e2.zip u-boot-imx-cb5473205206c7f14cbb1e747f28ec75b48826e2.tar.gz u-boot-imx-cb5473205206c7f14cbb1e747f28ec75b48826e2.tar.bz2 | |
Merge branch 'fixes' into cleanups
Conflicts:
board/atmel/atngw100/atngw100.c
board/atmel/atstk1000/atstk1000.c
cpu/at32ap/at32ap700x/gpio.c
include/asm-avr32/arch-at32ap700x/clk.h
include/configs/atngw100.h
include/configs/atstk1002.h
include/configs/atstk1003.h
include/configs/atstk1004.h
include/configs/atstk1006.h
include/configs/favr-32-ezkit.h
include/configs/hammerhead.h
include/configs/mimc200.h
Diffstat (limited to 'board/esd/mecp5200/mecp5200.c')
| -rw-r--r-- | board/esd/mecp5200/mecp5200.c | 22 |
1 files changed, 14 insertions, 8 deletions
diff --git a/board/esd/mecp5200/mecp5200.c b/board/esd/mecp5200/mecp5200.c index 6d776b7..3192450 100644 --- a/board/esd/mecp5200/mecp5200.c +++ b/board/esd/mecp5200/mecp5200.c @@ -32,6 +32,7 @@ #include <mpc5xxx.h> #include <pci.h> #include <command.h> +#include <netdev.h> #include "mt46v16m16-75.h" @@ -80,7 +81,7 @@ static void sdram_start(int hi_addr) /* * ATTENTION: Although partially referenced initdram does NOT make real use - * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE * is something else than 0x00000000. */ @@ -105,9 +106,9 @@ phys_size_t initdram(int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size(CFG_SDRAM_BASE, 0x80000000); + test1 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size(CFG_SDRAM_BASE, 0x80000000); + test2 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); @@ -142,9 +143,9 @@ phys_size_t initdram(int board_type) #if 0 /* find RAM size using SDRAM CS1 only */ sdram_start(0); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); sdram_start(1); - get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000); + get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); sdram_start(0); #endif /* set SDRAM CS1 size according to the amount of RAM found */ @@ -174,14 +175,14 @@ void flash_preinit(void) void flash_afterinit(ulong size) { - if (size == CFG_FLASH_SIZE) { + if (size == CONFIG_SYS_FLASH_SIZE) { /* adjust mapping */ *(vu_long *) MPC5XXX_BOOTCS_START = *(vu_long *) MPC5XXX_CS0_START = - START_REG(CFG_BOOTCS_START | size); + START_REG(CONFIG_SYS_BOOTCS_START | size); *(vu_long *) MPC5XXX_BOOTCS_STOP = *(vu_long *) MPC5XXX_CS0_STOP = - STOP_REG(CFG_BOOTCS_START | size, size); + STOP_REG(CONFIG_SYS_BOOTCS_START | size, size); } } @@ -259,3 +260,8 @@ void init_power_switch(void) __asm__ volatile ("sync"); } } + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} |