diff options
| author | Matthias Fuchs <matthias.fuchs@esd-electronics.com> | 2008-10-07 13:13:08 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-10-10 09:38:36 +0200 |
| commit | 6a133d6a00b1fc7b9257cd5925d8cb67f75ecda2 (patch) | |
| tree | 86f5ba54bc9ac53970cfc47c68554c892c7d9068 /board/esd/du440/du440.c | |
| parent | 35dd025c70fcc4389317db2f2a9d14795172137d (diff) | |
| download | u-boot-imx-6a133d6a00b1fc7b9257cd5925d8cb67f75ecda2.zip u-boot-imx-6a133d6a00b1fc7b9257cd5925d8cb67f75ecda2.tar.gz u-boot-imx-6a133d6a00b1fc7b9257cd5925d8cb67f75ecda2.tar.bz2 | |
ppc4xx: Fix DU440 GPIO configuration
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/esd/du440/du440.c')
| -rw-r--r-- | board/esd/du440/du440.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 8765cc1..5cff9f5 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -52,15 +52,15 @@ int board_early_init_f(void) * Setup the GPIO pins */ out_be32((void*)GPIO0_OR, 0x00000000 | CFG_GPIO0_EP_EEP); - out_be32((void*)GPIO0_TCR, 0x0000000f | CFG_GPIO0_EP_EEP); + out_be32((void*)GPIO0_TCR, 0x0000001f | CFG_GPIO0_EP_EEP); out_be32((void*)GPIO0_OSRL, 0x50055400); - out_be32((void*)GPIO0_OSRH, 0x550050aa); + out_be32((void*)GPIO0_OSRH, 0x55005000); out_be32((void*)GPIO0_TSRL, 0x50055400); out_be32((void*)GPIO0_TSRH, 0x55005000); out_be32((void*)GPIO0_ISR1L, 0x50000000); out_be32((void*)GPIO0_ISR1H, 0x00000000); out_be32((void*)GPIO0_ISR2L, 0x00000000); - out_be32((void*)GPIO0_ISR2H, 0x00000100); + out_be32((void*)GPIO0_ISR2H, 0x00000000); out_be32((void*)GPIO0_ISR3L, 0x00000000); out_be32((void*)GPIO0_ISR3H, 0x00000000); @@ -73,9 +73,9 @@ int board_early_init_f(void) CFG_GPIO1_LEDPOST | CFG_GPIO1_LEDDU); out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU); - out_be32((void*)GPIO1_OSRL, 0x5c280000); + out_be32((void*)GPIO1_OSRL, 0x0c280000); out_be32((void*)GPIO1_OSRH, 0x00000000); - out_be32((void*)GPIO1_TSRL, 0x0c000000); + out_be32((void*)GPIO1_TSRL, 0xcc000000); out_be32((void*)GPIO1_TSRH, 0x00000000); out_be32((void*)GPIO1_ISR1L, 0x00005550); out_be32((void*)GPIO1_ISR1H, 0x00000000); |