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| author | roy zang <tie-fei.zang@freescale.com> | 2007-02-12 11:24:27 +0800 |
|---|---|---|
| committer | Zang Tiefei <roy@bus.ap.freescale.net> | 2007-02-12 11:24:27 +0800 |
| commit | 30bddf2c46ab2e824f217a38db033118ac4622af (patch) | |
| tree | 2969155507e6902a7dddebad6c7c9ba259e816be /board/esd/cpci750/sdram_init.c | |
| parent | c1c52e38d35ff01f08b55377126c979a08fbdb1d (diff) | |
| parent | b0b1a920aebead0d44146e73676ae9d80fffc8e2 (diff) | |
| download | u-boot-imx-30bddf2c46ab2e824f217a38db033118ac4622af.zip u-boot-imx-30bddf2c46ab2e824f217a38db033118ac4622af.tar.gz u-boot-imx-30bddf2c46ab2e824f217a38db033118ac4622af.tar.bz2 | |
Merge branch 'master' into hpc2
Diffstat (limited to 'board/esd/cpci750/sdram_init.c')
| -rw-r--r-- | board/esd/cpci750/sdram_init.c | 41 |
1 files changed, 31 insertions, 10 deletions
diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c index 6bdfc1d..c094755 100644 --- a/board/esd/cpci750/sdram_init.c +++ b/board/esd/cpci750/sdram_init.c @@ -1504,6 +1504,8 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ { + int l, l1; + i = info->slot; DP (printf ("\n*** Running a MRS cycle for bank %d ***\n", i)); @@ -1511,20 +1513,39 @@ int setup_sdram (AUX_MEM_DIMM_INFO * info) /* map the bank */ memory_map_bank (i, 0, GB / 4); #if 1 /* test only */ - /* set SDRAM mode */ /* To_do check it */ + + tmp = GTREGREAD (SDRAM_MODE); + GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0); + GT_REG_WRITE (SDRAM_OPERATION, 0x4); + while (GTREGREAD (SDRAM_OPERATION) != 0) { + DP (printf + ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + } + + GT_REG_WRITE (SDRAM_MODE, tmp | 0x80); GT_REG_WRITE (SDRAM_OPERATION, 0x3); - check = GTREGREAD (SDRAM_OPERATION); - DP (printf - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + while (GTREGREAD (SDRAM_OPERATION) != 0) { + DP (printf + ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + } + l1 = 0; + for (l=0;l<200;l++) + l1 += GTREGREAD (SDRAM_OPERATION); + GT_REG_WRITE (SDRAM_MODE, tmp); + GT_REG_WRITE (SDRAM_OPERATION, 0x3); + while (GTREGREAD (SDRAM_OPERATION) != 0) { + DP (printf + ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + } /* switch back to normal operation mode */ - GT_REG_WRITE (SDRAM_OPERATION, 0); - check = GTREGREAD (SDRAM_OPERATION); - DP (printf - ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", - check)); + GT_REG_WRITE (SDRAM_OPERATION, 0x5); + while (GTREGREAD (SDRAM_OPERATION) != 0) { + DP (printf + ("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n")); + } + #endif /* test only */ /* unmap the bank */ memory_map_bank (i, 0, 0); |