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authorWolfgang Denk <wd@denx.de>2009-03-21 22:15:49 +0100
committerWolfgang Denk <wd@denx.de>2009-03-21 22:15:49 +0100
commitee1702d75a30d076139d1841383a1fa7220a0e11 (patch)
treeb008c231b7d5e4e52ac49aec9a49bc73413aaf30 /board/esd/cpci405
parente60beb13cf0135dc71c541021487b5ccc4d269cb (diff)
parentfaac4fd852e39cb1d7a740801b060e41aeacef1f (diff)
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Merge branch 'next' of ../next
Diffstat (limited to 'board/esd/cpci405')
-rw-r--r--board/esd/cpci405/cpci405.c8
-rw-r--r--board/esd/cpci405/u-boot.lds4
2 files changed, 5 insertions, 7 deletions
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index 0aca825..ccbe245 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -111,10 +111,10 @@ int board_early_init_f(void)
* First pull fpga-prg pin low,
* to disable fpga logic (on version 2 board)
*/
- out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
- out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
- out32(GPIO0_OR, 0); /* pull prg low */
+ out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
+ out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
+ out_be32((void *)GPIO0_OR, 0); /* pull prg low */
/*
* Boot onboard FPGA
diff --git a/board/esd/cpci405/u-boot.lds b/board/esd/cpci405/u-boot.lds
index 5d59761..8c01016 100644
--- a/board/esd/cpci405/u-boot.lds
+++ b/board/esd/cpci405/u-boot.lds
@@ -67,10 +67,8 @@ SECTIONS
PROVIDE (etext = .);
.rodata :
{
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
*(.eh_frame)
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }