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authorstroese <stroese>2003-04-04 16:52:57 +0000
committerstroese <stroese>2003-04-04 16:52:57 +0000
commitafcc4a7404fb258cb89d0a2eead57fef7230c73b (patch)
tree2a75fdea1ccfc339fb23ae0c1986dce50dcc345b /board/esd/cpci405/cpci405.c
parent9e7d5ebea9f8e847dccdc58627d2407308ea9a56 (diff)
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Changed CPCI405 to use CTS instead of DSR on PPC405 UART1.
Diffstat (limited to 'board/esd/cpci405/cpci405.c')
-rw-r--r--board/esd/cpci405/cpci405.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index dc498d5..b50716f 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -234,6 +234,7 @@ int misc_init_r (void)
bd_t *bd = gd->bd;
char * tmp; /* Temporary char pointer */
+ unsigned long cntrl0Reg;
#ifdef CONFIG_CPCI405_VER2
unsigned char *dst;
@@ -241,7 +242,6 @@ int misc_init_r (void)
int status;
int index;
int i;
- unsigned long cntrl0Reg;
/*
* On CPCI-405 version 2 the environment is saved in eeprom!
@@ -378,6 +378,12 @@ int misc_init_r (void)
#endif /* CONFIG_CPCI405_VER2 */
/*
+ * Select cts (and not dsr) on uart1
+ */
+ cntrl0Reg = mfdcr(cntrl0);
+ mtdcr(cntrl0, cntrl0Reg | 0x00001000);
+
+ /*
* Write ethernet addr in NVRAM for VxWorks
*/
tmp = (char *)CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS;