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| author | Wolfgang Denk <wd@denx.de> | 2009-03-21 22:15:49 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-03-21 22:15:49 +0100 |
| commit | ee1702d75a30d076139d1841383a1fa7220a0e11 (patch) | |
| tree | b008c231b7d5e4e52ac49aec9a49bc73413aaf30 /board/esd/common | |
| parent | e60beb13cf0135dc71c541021487b5ccc4d269cb (diff) | |
| parent | faac4fd852e39cb1d7a740801b060e41aeacef1f (diff) | |
| download | u-boot-imx-ee1702d75a30d076139d1841383a1fa7220a0e11.zip u-boot-imx-ee1702d75a30d076139d1841383a1fa7220a0e11.tar.gz u-boot-imx-ee1702d75a30d076139d1841383a1fa7220a0e11.tar.bz2 | |
Merge branch 'next' of ../next
Diffstat (limited to 'board/esd/common')
| -rw-r--r-- | board/esd/common/fpga.c | 14 | ||||
| -rw-r--r-- | board/esd/common/lcd.h | 14 | ||||
| -rw-r--r-- | board/esd/common/xilinx_jtag/ports.c | 5 |
3 files changed, 19 insertions, 14 deletions
diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c index 5232ddd..62c3243 100644 --- a/board/esd/common/fpga.c +++ b/board/esd/common/fpga.c @@ -24,6 +24,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <command.h> /* ------------------------------------------------------------------------- */ @@ -55,7 +56,7 @@ #define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */ #ifndef SET_FPGA -# define SET_FPGA(data) out32(GPIO0_OR, data) +# define SET_FPGA(data) out_be32((void *)GPIO0_OR, data) #endif #ifdef FPGA_PROG_ACTIVE_HIGH @@ -85,10 +86,10 @@ SET_FPGA(FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);} /* set data to 1 */ #ifndef FPGA_DONE_STATE -# define FPGA_DONE_STATE (in32(GPIO0_IR) & FPGA_DONE) +# define FPGA_DONE_STATE (in_be32((void *)GPIO0_IR) & FPGA_DONE) #endif #ifndef FPGA_INIT_STATE -# define FPGA_INIT_STATE (in32(GPIO0_IR) & FPGA_INIT) +# define FPGA_INIT_STATE (in_be32((void *)GPIO0_IR) & FPGA_INIT) #endif @@ -139,8 +140,11 @@ static int fpga_boot (const unsigned char *fpgadata, int size) * Setup port pins for fpga programming */ #ifndef CONFIG_M5249 - out32 (GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */ + out_be32 ((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */ + /* setup for output */ + out_be32 ((void *)GPIO0_TCR, + in_be32 ((void *)GPIO0_TCR) | + FPGA_PRG | FPGA_CLK | FPGA_DATA); #endif SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH); /* set pins to high */ diff --git a/board/esd/common/lcd.h b/board/esd/common/lcd.h index 3169e6b..01f6019 100644 --- a/board/esd/common/lcd.h +++ b/board/esd/common/lcd.h @@ -40,13 +40,13 @@ #define TRUE (!FALSE) #endif -#define S1D_WRITE_PALETTE(p,i,r,g,b) \ - { \ - ((volatile uchar*)(p))[palette_index] = (uchar)(i); \ - ((volatile uchar*)(p))[palette_value] = (uchar)(r); \ - ((volatile uchar*)(p))[palette_value] = (uchar)(g); \ - ((volatile uchar*)(p))[palette_value] = (uchar)(b); \ - } +#define S1D_WRITE_PALETTE(p,i,r,g,b) \ + { \ + out_8(&((uchar*)(p))[palette_index], (uchar)(i)); \ + out_8(&((uchar*)(p))[palette_index], (uchar)(r)); \ + out_8(&((uchar*)(p))[palette_index], (uchar)(g)); \ + out_8(&((uchar*)(p))[palette_index], (uchar)(b)); \ + } typedef struct { diff --git a/board/esd/common/xilinx_jtag/ports.c b/board/esd/common/xilinx_jtag/ports.c index 3ad94a5..ac0d7ac 100644 --- a/board/esd/common/xilinx_jtag/ports.c +++ b/board/esd/common/xilinx_jtag/ports.c @@ -32,6 +32,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include "ports.h" @@ -68,7 +69,7 @@ void setPort(short p,short val) } else { output &= ~JTAG_TCK; } - out32(GPIO0_OR, output); + out_be32((void *)GPIO0_OR, output); } } @@ -98,7 +99,7 @@ unsigned char readTDOBit(void) { unsigned long inputs; - inputs = in32(GPIO0_IR); + inputs = in_be32((void *)GPIO0_IR); if (inputs & JTAG_TDO) return 1; else |