Migrate esd 405EP boards to new NAND subsystem

Migrate esd 405EP boards to new NAND subsystem

-cleanup
-use correct io accessors (in/out_be32())

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>

2 files changed, 12 insertions, 32 deletions

diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile
index df48766..0d4ab2d 100644
--- a/board/esd/cms700/Makefile
+++ b/board/esd/cms700/Makefile
@@ -33,7 +33,10 @@ CPLD    = ../common/xilinx_jtag/lenval.o \
 	  ../common/xilinx_jtag/micro.o \
 	  ../common/xilinx_jtag/ports.o
 
-COBJS	= $(BOARD).o flash.o ../common/misc.o $(CPLD)
+COBJS	= $(BOARD).o flash.o \
+	../common/misc.o \
+	$(CPLD) \
+	../common/esd405ep_nand.o \
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
index cb04710..2cdd7be 100644
--- a/board/esd/cms700/cms700.c
+++ b/board/esd/cms700/cms700.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2005
+ * (C) Copyright 2005-2007
  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
  *
  * See file CREDITS for list of people who contributed to this
@@ -23,6 +23,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <command.h>
 #include <malloc.h>
 
@@ -68,9 +69,9 @@ int board_early_init_f (void)
 	/*
 	 * Reset CPLD via GPIO12 (CS3) pin
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET);
 	udelay(1000); /* wait 1ms */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET);
 	udelay(1000); /* wait 1ms */
 
 	return 0;
@@ -94,13 +95,7 @@ int misc_init_r (void)
  	/*
 	 * Setup and enable EEPROM write protection
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
-
-	/*
-	 * Set NAND-FLASH GPIO signals to default
-	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
 
 	return (0);
 }
@@ -153,11 +148,6 @@ long int initdram (int board_type)
 	mtdcr(memcfga, mem_mb0cf);
 	val = mfdcr(memcfgd);
 
-#if 0
-	printf("\nmb0cf=%x\n", val); /* test-only */
-	printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
 	return (4*1024*1024 << ((val & 0x000e0000) >> 17));
 }
 
@@ -180,17 +170,17 @@ int eeprom_write_enable (unsigned dev_addr, int state)
 		switch (state) {
 		case 1:
 			/* Enable write access, clear bit GPIO_SINT2. */
-			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP);
 			state = 0;
 			break;
 		case 0:
 			/* Disable write access, set bit GPIO_SINT2. */
-			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
 			state = 0;
 			break;
 		default:
 			/* Read current status back. */
-			state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+			state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP));
 			break;
 		}
 	}
@@ -235,19 +225,6 @@ U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
 
 /* ------------------------------------------------------------------------- */
 
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
-	nand_probe(CFG_NAND_BASE);
-	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
-		print_size(nand_dev_desc[0].totlen, "\n");
-	}
-}
-#endif
-
 void reset_phy(void)
 {
 #ifdef CONFIG_LXT971_NO_SLEEP