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authorStefan Roese <sr@denx.de>2009-09-09 16:25:29 +0200
committerStefan Roese <sr@denx.de>2009-09-11 10:35:58 +0200
commitd1c3b27525b664e8c4db6bb173eed51bfc8220de (patch)
treec00f3d0bcfbd5fcc1954cc9cefdbc4c9c41f41ea /board/esd/canbt
parente7963772eb78a6aa1fa65063d64eab3a8626daac (diff)
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ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/esd/canbt')
-rw-r--r--board/esd/canbt/canbt.c8
-rw-r--r--board/esd/canbt/flash.c10
2 files changed, 9 insertions, 9 deletions
diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c
index 2fe6b7b..418d3e2 100644
--- a/board/esd/canbt/canbt.c
+++ b/board/esd/canbt/canbt.c
@@ -52,16 +52,16 @@ const unsigned char fpgadata[] = {
int board_early_init_f (void)
{
- unsigned long cntrl0Reg;
+ unsigned long CPC0_CR0Reg;
int index, len, i;
int status;
/*
* Setup GPIO pins
*/
- cntrl0Reg = mfdcr (cntrl0) & 0xf0001fff;
- cntrl0Reg |= 0x0070f000;
- mtdcr (cntrl0, cntrl0Reg);
+ CPC0_CR0Reg = mfdcr (CPC0_CR0) & 0xf0001fff;
+ CPC0_CR0Reg |= 0x0070f000;
+ mtdcr (CPC0_CR0, CPC0_CR0Reg);
#ifdef FPGA_DEBUG
/* set up serial port with default baudrate */
diff --git a/board/esd/canbt/flash.c b/board/esd/canbt/flash.c
index 56c822e..224dde4 100644
--- a/board/esd/canbt/flash.c
+++ b/board/esd/canbt/flash.c
@@ -64,13 +64,13 @@ unsigned long flash_init (void)
flash_get_offsets (-size_b0, &flash_info[0]);
/* Re-do sizing to get full correct info */
- mtdcr(ebccfga, pb0cr);
- pbcr = mfdcr(ebccfgd);
- mtdcr(ebccfga, pb0cr);
+ mtdcr(EBC0_CFGADDR, PB0CR);
+ pbcr = mfdcr(EBC0_CFGDATA);
+ mtdcr(EBC0_CFGADDR, PB0CR);
base_b0 = -size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
- mtdcr(ebccfgd, pbcr);
- /* printf("pb1cr = %x\n", pbcr); */
+ mtdcr(EBC0_CFGDATA, pbcr);
+ /* printf("PB1CR = %x\n", pbcr); */
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,