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authorStefan Roese <sr@denx.de>2009-09-09 16:25:29 +0200
committerStefan Roese <sr@denx.de>2009-09-11 10:35:58 +0200
commitd1c3b27525b664e8c4db6bb173eed51bfc8220de (patch)
treec00f3d0bcfbd5fcc1954cc9cefdbc4c9c41f41ea /board/esd/apc405
parente7963772eb78a6aa1fa65063d64eab3a8626daac (diff)
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ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/esd/apc405')
-rw-r--r--board/esd/apc405/apc405.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
index 5a02155..46622a2 100644
--- a/board/esd/apc405/apc405.c
+++ b/board/esd/apc405/apc405.c
@@ -92,7 +92,7 @@ int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
int board_revision(void)
{
- unsigned long cntrl0Reg;
+ unsigned long CPC0_CR0Reg;
unsigned long value;
/*
@@ -100,8 +100,8 @@ int board_revision(void)
*/
/* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
- cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | 0x03800000);
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
@@ -113,7 +113,7 @@ int board_revision(void)
/*
* Restore GPIO settings
*/
- mtdcr(cntrl0, cntrl0Reg);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
switch (value) {
case 0x001c0000:
@@ -166,7 +166,7 @@ int board_early_init_f (void)
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks
*/
- mtebc(epcr, 0xa8400000); /* ebc always driven */
+ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
/*
* New boards have a single 32MB flash connected to CS0
@@ -174,12 +174,12 @@ int board_early_init_f (void)
*/
if (board_revision() >= 8) {
/* disable CS1 */
- mtebc(pb1ap, 0);
- mtebc(pb1cr, 0);
+ mtebc(PB1AP, 0);
+ mtebc(PB1CR, 0);
/* resize CS0 to 32MB */
- mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP_HWREV8);
- mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR_HWREV8);
+ mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
+ mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
}
return 0;
@@ -209,7 +209,7 @@ int misc_init_r(void)
int status;
int index;
int i;
- unsigned long cntrl0Reg;
+ unsigned long CPC0_CR0Reg;
char *str;
uchar *logo_addr;
ulong logo_size;
@@ -219,8 +219,8 @@ int misc_init_r(void)
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
*/
- cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
@@ -265,7 +265,7 @@ int misc_init_r(void)
}
/* restore gpio/cs settings */
- mtdcr(cntrl0, cntrl0Reg);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
puts("FPGA: ");