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| author | Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com> | 2012-08-09 18:29:57 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:19 +0200 |
| commit | 6995a2893718a54cbd255ea3dd9b6d7306e30cf2 (patch) | |
| tree | cd4a9e07c0a76c4d6f719e07c2c7dffe3ae83f65 /board/enbw/enbw_cmc | |
| parent | 25f8bf6eff9e66df850301c5e9e5259807e286f0 (diff) | |
| download | u-boot-imx-6995a2893718a54cbd255ea3dd9b6d7306e30cf2.zip u-boot-imx-6995a2893718a54cbd255ea3dd9b6d7306e30cf2.tar.gz u-boot-imx-6995a2893718a54cbd255ea3dd9b6d7306e30cf2.tar.bz2 | |
am33xx evm: Update secure_emif_sdram_config during ddr init
This patch updates secure_emif_sdram_config with the
same value written to sdram_config during ddr3 initialization.
During suspend/resume, this value is copied into sdram_config.
With this, a write to sdram_config at the end of resume sequence
which triggers an init sequence can be avoided.
Without this register write in place, the DDR_RESET line goes
low for a few cycles during resume which is a violation of the
JEDEC spec.
Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
Diffstat (limited to 'board/enbw/enbw_cmc')
0 files changed, 0 insertions, 0 deletions