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author | Aneesh V <aneesh@ti.com> | 2012-02-16 03:40:15 +0000 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-02-27 21:19:25 +0100 |
commit | f1f2c3ca9f837985cc1f4bc3821ac1763430cdcf (patch) | |
tree | 53e64e96d5547d90fef5971855c35e694e499908 /board/egnite | |
parent | c21052b9947b0376db094f6143b8d584bdcc287d (diff) | |
download | u-boot-imx-f1f2c3ca9f837985cc1f4bc3821ac1763430cdcf.zip u-boot-imx-f1f2c3ca9f837985cc1f4bc3821ac1763430cdcf.tar.gz u-boot-imx-f1f2c3ca9f837985cc1f4bc3821ac1763430cdcf.tar.bz2 |
armv7: omap3: leave outer cache enabled
Mainline kernel for OMAP3 doesn't enable L2 cache
It expects L2$ to be enabled by ROM-code/bootloader.
Leaving L2$ enabled can be troublesome in cases where
the L2 cache is not under CP15 control, such as in
Cortex-A9. This problem is explained in detail in
the commit dc7100f4080952798413fb63bb4134b22c57623a
However, this problem doesn't apply to Cortex-A8
because L2$ in Cortex-A8 is under CP15 control and
hence the generic armv7 maintenance opertions work
for it.
As such we can make an exception for OMAP3 and
leave the L2$ enabled when we jump to kernel. This
is done by removing the strongly-linked implementation
of v7_outer_cache_disable() and allowing it to fall
back to the weakly linked implementation that doesn't
do anything.
Signed-off-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'board/egnite')
0 files changed, 0 insertions, 0 deletions