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| author | Marek Vasut <marek.vasut@gmail.com> | 2011-09-28 02:19:57 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-12-06 23:59:40 +0100 |
| commit | 55723954829f30cf148924ee55d10b1662551edc (patch) | |
| tree | 9272d59f87ae6d61c70b2127d4e385fc1183fa34 /board/efikamx/efikamx.c | |
| parent | 5acc90729488328665ebee7bc7ae2fb6c9e08c3a (diff) | |
| download | u-boot-imx-55723954829f30cf148924ee55d10b1662551edc.zip u-boot-imx-55723954829f30cf148924ee55d10b1662551edc.tar.gz u-boot-imx-55723954829f30cf148924ee55d10b1662551edc.tar.bz2 | |
Efika: Configure additional regulators for HDMI output
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'board/efikamx/efikamx.c')
| -rw-r--r-- | board/efikamx/efikamx.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c index b78bf6c..3d2cc1a 100644 --- a/board/efikamx/efikamx.c +++ b/board/efikamx/efikamx.c @@ -226,7 +226,7 @@ static void power_init(void) /* Set core voltage to 1.1V */ pmic_reg_read(p, REG_SW_0, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; + val = (val & ~SWx_VOLT_MASK) | SWx_1_200V; pmic_reg_write(p, REG_SW_0, val); /* Setup VCC (SW2) to 1.25 */ @@ -260,18 +260,23 @@ static void power_init(void) (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); pmic_reg_write(p, REG_SW_5, val); - /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */ + /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */ pmic_reg_read(p, REG_SETTING_0, &val); val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); - val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6; + val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6; pmic_reg_write(p, REG_SETTING_0, val); /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ pmic_reg_read(p, REG_SETTING_1, &val); val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); - val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775; + val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15; pmic_reg_write(p, REG_SETTING_1, val); + /* Enable VGEN1, VGEN2, VDIG, VPLL */ + pmic_reg_read(p, REG_MODE_0, &val); + val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN; + pmic_reg_write(p, REG_MODE_0, val); + /* Configure VGEN3 and VCAM regulators to use external PNP */ val = VGEN3CONFIG | VCAMCONFIG; pmic_reg_write(p, REG_MODE_1, val); @@ -279,7 +284,7 @@ static void power_init(void) /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | - VVIDEOEN | VAUDIOEN | VSDEN; + VVIDEOEN | VAUDIOEN | VSDEN; pmic_reg_write(p, REG_MODE_1, val); pmic_reg_read(p, REG_POWER_CTL2, &val); |