summaryrefslogtreecommitdiff
path: root/board/eXalion
diff options
context:
space:
mode:
authorStefan Roese <sr@denx.de>2007-12-06 05:58:43 +0100
committerStefan Roese <sr@denx.de>2007-12-06 05:58:43 +0100
commita27044b14a9e93678a82d7b35f202b93e7687abc (patch)
treec4a0a54d0fcc9cbde8820ed77c61d3cff2e714f5 /board/eXalion
parenta90921f71d225bf9e0f0fc7b8beadeb8001bf78a (diff)
downloadu-boot-imx-a27044b14a9e93678a82d7b35f202b93e7687abc.zip
u-boot-imx-a27044b14a9e93678a82d7b35f202b93e7687abc.tar.gz
u-boot-imx-a27044b14a9e93678a82d7b35f202b93e7687abc.tar.bz2
ppc4xx: Enable hardware-fix for PCI/DMA errata on AMCC 440SP/SPe boards
This patch enables the hardware-fix for the PCI/DMA errata's 19+22 by setting the FIXD bit in the SDR0_MFR register. Here a description of the symptoms: Problem Description ------------------------------ If a DMA is performed between memory and PCI with the DMA 1 Controller using prefetch, and as a result uses a special purpose buffer selected by the PCIXn Bridge Options 1 Register (PCIXn_BRDGOPT1[RBP7] - bits 31-29), the first part of the transfer sequence is performed twice. The PPC440SPe PCI Controller requests more data than was needed such that in the case of enforce memory protection, a host CPU exception can occur. No data is corrupted, because data transfer is stopped in the PCI Controller. Prefetch enable is specified by setting DMA Configuration Register (I2O0_DMAx_CFG[DXEPD] - bit 31) to 0. Behavior that may be observed in a running system --------------------------------------------------------------------------- 1. DMA performance is decreased because of the double access on the PCI bus interface. 2. If an illegal access to some address on the PCI bus is detected at the system level, a machine check or similar system error may occur. Workarounds Available ---------------------------------- 1. Do not program prefetch. Note that a prefetch command cannot be programmed without selecting a special purpose buffer. 2. To avoid crossing a physical boundary of the PCI slave device, add 512 bytes of address to the PCI address range. This patch was originally provided by Pravin M. Bathija <pbathija@amcc.com> from AMCC and slighly changed. Signed-off-by: Pravin M. Bathija <pbathija@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/eXalion')
0 files changed, 0 insertions, 0 deletions