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| author | Grzegorz Bernacki <gjb@semihalf.com> | 2009-03-17 10:06:40 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-03-20 22:39:14 +0100 |
| commit | 5c4fa9b474af95d60f019ec6369cbe77b9dab4b5 (patch) | |
| tree | b5fce8725007726afc47808b364b1e3b9cbde652 /board/digsy_mtc/is42s16800a-7t.h | |
| parent | ff7dc067369e30066744f096995aef7d97574d15 (diff) | |
| download | u-boot-imx-5c4fa9b474af95d60f019ec6369cbe77b9dab4b5.zip u-boot-imx-5c4fa9b474af95d60f019ec6369cbe77b9dab4b5.tar.gz u-boot-imx-5c4fa9b474af95d60f019ec6369cbe77b9dab4b5.tar.bz2 | |
Add support for the digsy MTC board.
This is the InterControl custom device based on the MPC5200B chip.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Diffstat (limited to 'board/digsy_mtc/is42s16800a-7t.h')
| -rw-r--r-- | board/digsy_mtc/is42s16800a-7t.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/board/digsy_mtc/is42s16800a-7t.h b/board/digsy_mtc/is42s16800a-7t.h new file mode 100644 index 0000000..1873ea7 --- /dev/null +++ b/board/digsy_mtc/is42s16800a-7t.h @@ -0,0 +1,28 @@ +/* + * (C) Copyright 2004-2009 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#define SDRAM_MODE 0x00CD0000 +#define SDRAM_CONTROL 0x505F0000 +#define SDRAM_CONFIG1 0xD2322900 +#define SDRAM_CONFIG2 0x8AD70000 + |