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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-10-16 15:01:15 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:03 +0200 |
| commit | 6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch) | |
| tree | ae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /board/delta/nand.c | |
| parent | 71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff) | |
| download | u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.zip u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.gz u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.bz2 | |
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'board/delta/nand.c')
| -rw-r--r-- | board/delta/nand.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/board/delta/nand.c b/board/delta/nand.c index ceb798b..14382f5 100644 --- a/board/delta/nand.c +++ b/board/delta/nand.c @@ -28,19 +28,19 @@ #include <nand.h> #include <asm/arch/pxa-regs.h> -#ifdef CFG_DFC_DEBUG1 +#ifdef CONFIG_SYS_DFC_DEBUG1 # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args) #else # define DFC_DEBUG1(fmt, args...) #endif -#ifdef CFG_DFC_DEBUG2 +#ifdef CONFIG_SYS_DFC_DEBUG2 # define DFC_DEBUG2(fmt, args...) printf(fmt, ##args) #else # define DFC_DEBUG2(fmt, args...) #endif -#ifdef CFG_DFC_DEBUG3 +#ifdef CONFIG_SYS_DFC_DEBUG3 # define DFC_DEBUG3(fmt, args...) printf(fmt, ##args) #else # define DFC_DEBUG3(fmt, args...) @@ -206,7 +206,7 @@ static void wait_us(unsigned long us) static void dfc_clear_nddb(void) { NDCR &= ~NDCR_ND_RUN; - wait_us(CFG_NAND_OTHER_TO); + wait_us(CONFIG_SYS_NAND_OTHER_TO); } /* wait_event with timeout */ @@ -217,9 +217,9 @@ static unsigned long dfc_wait_event(unsigned long event) if(!event) return 0xff000000; else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD)) - timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; + timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ; else - timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ; + timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ; while(1) { ndsr = NDSR; @@ -242,7 +242,7 @@ static void dfc_new_cmd(void) int retry = 0; unsigned long status; - while(retry++ <= CFG_NAND_SENDCMD_RETRY) { + while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) { /* Clear NDSR */ NDSR = 0xFFF; @@ -433,8 +433,8 @@ int board_nand_init(struct nand_chip *nand) /* turn on the NAND Controller Clock (104 MHz @ D0) */ CKENA |= (CKENA_4_NAND | CKENA_9_SMC); -#undef CFG_TIMING_TIGHT -#ifndef CFG_TIMING_TIGHT +#undef CONFIG_SYS_TIMING_TIGHT +#ifndef CONFIG_SYS_TIMING_TIGHT tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1), DFC_MAX_tCH); tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1), @@ -473,7 +473,7 @@ int board_nand_init(struct nand_chip *nand) DFC_MAX_tWHR); tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2), DFC_MAX_tAR); -#endif /* CFG_TIMING_TIGHT */ +#endif /* CONFIG_SYS_TIMING_TIGHT */ DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR); |