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author | Zhang Jiejing <jiejing.zhang@freescale.com> | 2012-12-11 15:23:46 +0800 |
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committer | Zhang Jiejing <jiejing.zhang@freescale.com> | 2012-12-11 16:00:31 +0800 |
commit | 07663772b10318e3d7f0aa3e410f0ff840780806 (patch) | |
tree | fe7a9677fb3b04506e3c4cf76f0a9ec50e66e661 /board/dbau1x00 | |
parent | 0daf8bc6b77575581936a59e18476c48742669f0 (diff) | |
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ENGR00235817 mx6: use SNVS LPGPR register to store boot mode value.
After using POR reset, the content in SRC will be reset.
See RM: 63.5.1.2.3 IPP_RESET_B(POR)
Because POR reset will reset most of register in IC, so use
SNVS_LP General Purpose Register (LPGPR) to store the boot mode value.
Below copy from SNVS_BlockGuide.pdf:
The SNVS_LP General Purpose Register provides a 32 bit read write
register, which can be used by any application for retaining 32 bit
data during a power-down mode
This Patch will use [7,8] bits of this register.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
Diffstat (limited to 'board/dbau1x00')
0 files changed, 0 insertions, 0 deletions