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authorKumar Gala <galak@kernel.crashing.org>2006-04-20 12:25:10 -0500
committerKumar Gala <galak@kernel.crashing.org>2006-04-20 12:25:10 -0500
commitb86d7622b33892b1dafe761a7a9eaeeab9f3816b (patch)
tree56b1b6fc978166abce4afa8e9dee0af94bfc3cd6 /board/dbau1x00/lowlevel_init.S
parentf8edca2e9a128f526b1fe6f997f7adb852cf5b3c (diff)
parent56a4a63c106cc317fc0fe42686a99416fc469f5b (diff)
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Merge branch 'master' of rsync://rsync.denx.de/git/u-boot
Diffstat (limited to 'board/dbau1x00/lowlevel_init.S')
-rw-r--r--board/dbau1x00/lowlevel_init.S5
1 files changed, 4 insertions, 1 deletions
diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S
index 7afd584..14a7846 100644
--- a/board/dbau1x00/lowlevel_init.S
+++ b/board/dbau1x00/lowlevel_init.S
@@ -185,6 +185,8 @@ tlbloop:
bne t0, t2, tlbloop
nop
+#endif /* CONFIG_DBAU1550 */
+
/* First setup pll:s to make serial work ok */
/* We have a 12 MHz crystal */
li t0, SYS_CPUPLL
@@ -205,6 +207,7 @@ tlbloop:
sw t1, 0(t0) /* aux pll */
sync
+#ifdef CONFIG_DBAU1550
/* Static memory controller */
/* RCE0 - can not change while fetching, do so from icache */
move t2, ra /* Store return address */
@@ -237,7 +240,7 @@ noCacheJump:
sw t1, 0(t0)
#else /* CONFIG_DBAU1550 */
li t0, MEM_STTIME0
- li t1, 0x00014C0F
+ li t1, 0x040181D7
sw t1, 0(t0)
/* RCE0 AMD 29LV640M MirrorBit Flash */