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| author | Heiko Schocher <hs@pollux.denx.de> | 2006-04-11 14:53:29 +0200 |
|---|---|---|
| committer | Heiko Schocher <hs@pollux.denx.de> | 2006-04-11 14:53:29 +0200 |
| commit | ad88297e2f14220f34417d1304d256285887aed4 (patch) | |
| tree | 8539431105a49ca7918ac58af5d743289c193432 /board/dbau1x00/lowlevel_init.S | |
| parent | bb74140defaff27ccd4c7f8ecfec3244f5890777 (diff) | |
| download | u-boot-imx-ad88297e2f14220f34417d1304d256285887aed4.zip u-boot-imx-ad88297e2f14220f34417d1304d256285887aed4.tar.gz u-boot-imx-ad88297e2f14220f34417d1304d256285887aed4.tar.bz2 | |
* Fix dbau1x00 Board
- Fix dbau1x00 boards broken by dbau1550 patch
PLL:s were not set for boards other than 1550.
Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST.
Default boot is now bootp for cards other than 1550.
Patch by Thomas Lange Aug 10 2005
Diffstat (limited to 'board/dbau1x00/lowlevel_init.S')
| -rw-r--r-- | board/dbau1x00/lowlevel_init.S | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S index 7afd584..14a7846 100644 --- a/board/dbau1x00/lowlevel_init.S +++ b/board/dbau1x00/lowlevel_init.S @@ -185,6 +185,8 @@ tlbloop: bne t0, t2, tlbloop nop +#endif /* CONFIG_DBAU1550 */ + /* First setup pll:s to make serial work ok */ /* We have a 12 MHz crystal */ li t0, SYS_CPUPLL @@ -205,6 +207,7 @@ tlbloop: sw t1, 0(t0) /* aux pll */ sync +#ifdef CONFIG_DBAU1550 /* Static memory controller */ /* RCE0 - can not change while fetching, do so from icache */ move t2, ra /* Store return address */ @@ -237,7 +240,7 @@ noCacheJump: sw t1, 0(t0) #else /* CONFIG_DBAU1550 */ li t0, MEM_STTIME0 - li t1, 0x00014C0F + li t1, 0x040181D7 sw t1, 0(t0) /* RCE0 AMD 29LV640M MirrorBit Flash */ |